PD term and PV term

What is a "Keepout region" in Floorplanning?

• Areas where wire connections cannot pass through
• Area containing important functional blocks
• Area where functional blocks cannot be placed
• Areas with high signal delay

In Floorplanning, what does the term "aspect ratio" refer to?

• Ratio between the area of ​​the block and the area of ​​the entire chip
• Ratio between length and width of a functional block
• Ratio between the number of transistors and chip area
• Ratio between power consumption and chip performance

"Congestion map" in Placement is used to:

• Display the global routing results
• Show areas with high cell density
• Show high latency areas
• Displays the power consumption of the cells

In Placement, what does "timing-driven placement" mean?

• Place cells based on capacity requirements
• Place cells based on area requirements
• Place cells based on signal delay requirements
• Place cells based on design requirements

The main goal of CTS are

• Maximize skew & Maximize latency of design
• Maximize skew & Minimize latency of design
• Minimize skew & Maximize latency of design
• Minimize skew & minimize latency of design

Which kind of pin that allow clock net pass that pins ?

• Explicit stop pins
• Clock gating pins
• Sink pins
• Through pins

The term "global routing" refers to:

• Determine the location of cells on the chip
• Perform the virtual path of the wire connections
• Optimize the power consumption of cells
• Analyze signal delay

"Timing closure" in Routing refers to:

• Make sure all signals have delays within allowable limits
• Make sure all signals have power consumption within allowable limits
• Make sure all signals are connected properly
• Make sure all cells are in the correct position

In Routing, "shielding" is used to protect ... from signal interference

• Cells
• Sources
• Transistors
• Connecting wires

DRC stands for:

• Design Rule Check
• Data Rule Check
• Design Routing Check
• Data Routing Check