Veriog Module1

Consider the following Verilog code segment:

wire [5:0] A, B;

wire C; assign C = ^A;

If the values of A and B are 5'b10011 and 5'b01110 respectively,

what will be the value of {A[3:1], 2{C}, B[2:0]}

• 00100110

• 00111110

• 01111110

• None of these

Which combinational logic is generated by the following code segment?

input I0,I1;

input sel;

output f;

assign f = sel ? I1 : I0;

• 1X2 Demultiplexer

• 2x1 multiplexer

• 4x1 multiplexer

• tri state buffer

What combinational circuit do the following verilog module implement?

module example(a,b,c,f1,f2);

input a,b,c;

output f1,f2;

wire w1,w2,w3;

xor x1(w1,a,b);

xor x2(f1,w1,c);

and a1(w2,a,b);

and a2(w3,w1,c);

or(f2,w2,w3);

endmodule

• full adder

• Half adder

• Multiplexer

• 3 to 8 decoder

How will the number -8'd5 (in Verilog) be internally represented as bits?

•  1111 1110

•  1111 1100

•  1111 0000

•  1111 1011

Which of the following is a system task?

•  always block

   

• initial block

•  $display

•  assign statement

Which of the following does not represent a behavioral representation for the function

f = A.B +B.C + C.A?

• A truth table of the function f

• The Verilog specification: assign f = (A & B) | (B & C) | (C & A);

• A netlist consisting of three 2-input AND and one 3-input OR gate

• None of these

For the following Verilog code segment, if the initial value of IR is 2D00 023A (in hexadecimal), what will be the value of “memaddr” in decimal?

wire [31:0] IR;

wire [7:0] opcode;

wire [23:0] address;

wire [23:0] memaddr;

assign opcode = IR[31:24];

assign address = IR[23:0];

assign memaddr = address + 100;

• 685

• 670

• 723

• None of these

When does the $monitor statement in a Verilog test bench print the specified values?

• At the start of the simulation.

  .

• When the $monitor statement is first encountered.

• Whenever the value of any of the specified variables change.

• None of the above

If the 8-bit variable “data” declared as “reg [7:0] data” is initialized to 8’b01100101, what will be its value after execution of the following code segment?

always @(posedge clock)

begin

data[6:0] <= data[6:0] >> 1;

data[7] <= data[0];

• 8’b10110010

• 8’b00110010

• 8’b01110010

• None of these.

Which of the following statements are true?

• The $display command prints the values of the text / variables as soon as it is executed.

• The $display command prints the values of the text / variables when one or more of the specified variables changes value.

• The $monitor command prints the values of the text / variables as soon as it is executed.

• The $monitor command prints the values of the text / variables when one or more of the specified variables changes value.