
Digital system design
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1.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
In clock signal 0 to 1 transition is called
- ve edge
+ve edge
Level
Falling edge
2.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
A single Flip flop is a
1 bit storage
2 bit storage
Combinational circuit
n bit storage
3.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
In RS flip flop R= 0 S=0 and Q(t)=1 then the next state Q(t+1)=
0
X
Z
1
4.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
Which of the following flip flop has toggle condition
JK
RS
SR
D
5.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
Which of the following is data selector
Demux
Mux
Adder
Decoder
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