KuisBab6&7

A flip-flop is a ________ element that stores a binary digit as a low or high voltage. With an RS latch a high S and a low R sets the output to ________; a low S and a high R ________ the output to low.

• combinational, high, sets

• sequential, high, resets

• memory, low, reset

• memory, high, reset

With a NAND latch a low R and a low S produce a ________ condition. This is why R and S are kept high when inactive. One use for latches is switch debouncers; they eliminate the effects of ________ bounce.

• race, contact

• high, noise

• set, noise

• memory, race

Computers use thousands of flip-flops. To coordinate the overall action, a common signal called the ________ is sent to each flip-flop. With positive clocking the clock signal must be ________ for the flip-flop to respond. Positive and negative clocking are also called level clocking because the flip-flop responds to the ________ of the clock, either high or low.

• data, present, frequency

• clock, active, edge

• clock, high, level

• pulse, present, frequency

In a D latch, data bit D drives the S input of a latch, and the complement D drives the R input; therefore, a high D ________ the latch and a low D resets it. Since R and S are always in opposite states in a D latch, a ________ coordination is impossible.

• locks, clock

• sets, race

• resets, race

• activates, set

With a positive-edge-triggered D flip-flop, the data bit is sampled and stored on the ______ edge of the clock pulse. Preset and clear inputs are often called ______ set and ______ reset. These inputs override the other inputs; they have first priority. When preset goes low. the Q output goes ______ and stays there no matter what the D and CLK inputs are doing

• phase, asynchronous, synchronous, high

• edge, synchronous, asynchronous, low

• rising, direct, direct, high

• phase, asynchronous, synchronous, high

In a flip-flop, propagation delay time is the amount of time it takes for the ________ to change after the clock edge has struck. Setup time is the amount of time an input signal must be present ________ the clock edge strikes. Hold time is the amount of time an input signal must be present ________ the clock edge strikes.

• signal, during, before

• output, before, after

• state, during, before

• output, after, after

In a positive-edge-triggered JK flip-flop, a low J and a low K produce the ________ state. A high J and a high K mean that the output will ________ on the rising edge of the clock.

• inactive, toggle

• toggle, set

• hold, toggle

• reset, toggle

With a JK master-slave flip-flop the master is cocked when the clock is ________, and the slave is triggered when the clock is ________. This type of flip-flop is usually level-clocked instead of edge-triggered. For this reason, J and K are normally kept ________ while the clock is high.

• active, inactive, toggle

• high, low, inactive

• high, low, reset

• high, low, constant

When the LOAD input of a buffer register is active, the input word is stored on the next positive ______ edge. If LOAD then becomes inactive, the input word can change without affecting the ______ word.

• clock, stored

• clock, word

• clock, output

• • edge, stored

A shift register moves the ______ left or right. Serial loading means storing a word in a shift register by entering ______ bit per clock pulse. With parallel or broadside loading, it takes only one ______ pulse to load the input word.

• bits, clock, signal

• bits, 1, clock

• word, 1, input

• input, 1, clock