Verilog Module 3

What function does the following switch-level model realize?

module some_gate (in1, in2, out);

input in1, in2;

output out;

supply1 vplus;

supply0 vgnd;

wire t;

pmos (t, vplus, in1);

pmos (out, t, in2);

nmos (out, vgnd, in1);

nmos (out, vgnd, in2);

endmodule

• NAND

• Exclusive OR

• AND

• None of these

Suppose we are constructing a 16-to-1 multiplexer using cmos switches. In addition to four NOT gates, the number of cmos switches required will be ……

Which of the following statements is/are false?

• A tranif0 switch allows bidirectional flow of data between the two end terminals when the control signal is 0.

• A tranif0 switch allows bidirectional flow of data between the two end terminals when the control signal is 1.

• A tranif1 switch allows bidirectional flow of data between the two end terminals when the control signal is 0.

• A tranif1 switch allows bidirectional flow of data between the two end terminals when the control signal is 1.

Which of the following is/are true for user defined primitives in Verilog?

• Can be used to specify a combinational circuit with any number of outputs.

• Can be used to specify a combinational circuit with a single output.

• Can be used to specify a finite state machine with one or two state variables

• Can be used to specify a finite state machine with only one state variable.

Which of the following is/are not true for “generate” blocks?

• Multiple copies of code blocks are generated dynamically before simulation or synthesis.

• Can be used to instantiate multiple copies of some module.

• Must be used along with a variable of type “genvar”.

• All of these

What does the following Verilog module do?

module xor_bitwise (f, a, b);

parameter N = 16;

input [N-1:0] a, b;

output [N-1:0] f;

genvar p;

generate for (p=0; p<N; p=p+1)

begin

xorlp

xor XG(f[p],a[p],b[p]);

end

endgenerate

endmodule

• Generates the sum of the two N-bit numbers “a” and “b”, and stores it in “f”

• Performs the bitwise XOR of “a” and “b”, and stores it in “f”

• Computes whether the number of bits in “a” and “b” are odd

• None of these

What will the following code segment generate on synthesis?

always @(posedge clock)

begin

data3 <= din;

data2 <= data3;

data1 <= data2;

data0 <= data1;

end

• Four D flip-flops all fed with the data “din”.

• A 4-bit shift register.

• A 4-bit parallel-in parallel-out register.

• None of these.

What will the following code segment generate on synthesis, assuming that the four variables data0, data1, data2 and data3 map into four latches / flip-flops? always @(posedge clock)

begin

data3 = din;

data2 = data3;

data1 = data2;

data0 = data1;

end

• Four D flip-flops all fed with the data “din”

• A 4-bit shift register

• A 4-bit parallel-in parallel-out register.

• None of these.