Paper 1:Review_Revisions

Identify three registers that may be used in the Von Neumann model of a computer system.

• MAR, MDR, PC

• CPU, GPU, ALU

• RAM, ROM, Cache

• BIOS, OS, Application

Identify the two other stages of processing instructions besides the decode stage.

• Fetch and Execute

• Store and Write

• Load and Run

• Compile and Debug

Identify the component of the CPU responsible for decoding instructions.

• ALU

• Control Unit

• Register

• Cache

Why would a programmer use both an interpreter and a compiler?

• To translate high-level language into low-level language

• To convert binary code into machine code

• To run the code on different operating systems

• To improve security of the program

What are three advantages of using a high-level language over a low-level language?

• Easier to understand, debug, and maintain

• Uses more memory, is harder to debug, and runs slower

• Directly interacts with hardware, requires no interpreter, and is more secure

• Needs less storage, is optimized for speed, and runs only on Linux

How is data encrypted using symmetric encryption before transmission?

• It uses a single key for both encryption and decryption

• It uses separate keys for encryption and decryption

• It converts data into binary before sending

• It sends data as plain text with a hash

Which three methods can be used to secure data stored in an office?

• Firewall, Passwords, Physical Security (e.g., CCTV)

• Cloud backup, Email forwarding, USB encryption

• Disabling the internet, Using open-source software, Encrypting emails

• Installing antivirus, Printing data, Using Bluetooth transfers

Identify the given logic circuits.

• NAND

• AND

• OR

• XOR

Identify the given logic circuits.

• NAND

• AND

• NOR

• XOR

Complete the truth table for the given logic statement:

X = (((A OR C) AND (NOT A AND NOT C)) XOR B)

• 0 0 0 0

  1 1 0 1

  0 1 0 1

  0 1 1 1

  1 0 0 0

  1 0 1 0

  0 0 1 0

  1 1 1 1

• 1 1 1 1

  0 0 0 0

  0 0 1 0

  0 1 0 1

  0 1 1 1

  1 0 0 0

  1 0 1 0

  1 1 0 1

• 0 0 0 0

  0 0 1 0

  0 1 0 1

  0 1 1 1

  1 0 0 0

  1 0 1 0

  1 1 0 1

  1 1 1 1

• 1 1 1 1

  0 0 0 0

  1 0 0 0

  0 1 0 1

  0 1 1 1

  0 0 1 0

  1 0 1 0

  1 1 0 1