CMOS Logic Gates Quiz

Which configuration best describes a CMOS NAND gate?

• PMOS in series, NMOS in parallel

• PMOS in parallel, NMOS in series

• All PMOS only

• NMOS and PMOS in series

In a 2-input CMOS NOR gate, the pull-down network (PDN) is formed by:

• NMOS transistors in parallel

• PMOS transistors in parallel

• NMOS in series

• One NMOS and one PMOS

The output of a CMOS NAND gate is LOW only when:

• Any input is LOW

• All inputs are HIGH

• All inputs are LOW

• One input is HIGH

The output of a CMOS NOR gate is HIGH only when:

• All inputs are HIGH

• Any input is HIGH

• All inputs are LOW

• One input is HIGH

What is the minimum number of transistors required to implement a 2-input CMOS NAND gate?

• 2

• 4

• 6

• 3

The pull-up network in a CMOS NAND gate consists of:

• NMOS in parallel

• PMOS in parallel

• PMOS in series

• NMOS in series

Why is CMOS logic preferred over NMOS logic for building gates like NAND and NOR?

• Fewer transistors

• Higher speed only

• Lower static power consumption

• Simpler layout

In CMOS logic, logic '0' is passed more strongly by:

• PMOS

• NMOS

• Both equally

• Depends on fan-out

In a CMOS NOR gate, the PMOS transistors are connected in:

• Parallel

• Series

• Cross-coupled

• Cascode

Which logic gate has the worst case pull-up delay in CMOS logic?

• Inverter

• NAND

• NOR

• XOR