CPP110 PRELIM EXAM

The purpose of this module is to introduce High Definition of Language. The module discusses the digital logic design evolution and the basic ASIC design flow.

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Digital circuit design has evolved rapidly over the last 25 years. The earliest digital circuits were designed with microcontrollers and FPGAs.

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Computer Aided Design (CAD) techniques began to evolve to verify digital design functionality. These CAD techniques could already handle billions of transistors during their early development.

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Programming languages like FORTRAN, Pascal, and C are sequential in nature. HDLs allowed designers to model concurrency of processes in hardware.

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Logic synthesis tools can convert designs automatically to fabrication technology. If new technology emerges, designers must redesign their circuits from scratch.

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In a bottom-up design methodology, we define the top-level block first. In a bottom-up methodology, we secondarily identify building blocks and create bigger cells.

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Verilog is both a data and a natural language. Internals of modules can be defined at three levels of abstraction.

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The dataflow level is the highest level of abstraction in Verilog HDL. At this level, a module is implemented worrying about the hardware details.

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The gate level is the second bottom level of abstraction in Verilog. At this level, modules are implemented in terms of switches, storage nodes, etc.

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A module may consist of a set of lower-level blocks. Typically, elements are grouped into modules to provide common functionality.

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