System Verilog Assessment 4

Which keyword is used to define a concurrent assertion in SystemVerilog?

• 1. assert

• cover

• sequence

• property

What does an assertion do during simulation?

• 1. Optimizes code

• 1. Checks expected behavior

• Synthesizes logic

• 1. Generates waveform

Which of the following is a type of assertion in SystemVerilog?

• immediate

• static

• soft

• dynamic

Which construct is used to define temporal behavior in assertions?

• sequence

• task

• initial

• always

Which construct is used to define temporal behavior in assertions?

• assert property (a |->b);

• assert (a == b);

• assert sequence (a ##1 b);

• assert property (a && b);

What does ## represent in a sequence?

• Logical AND

• Concatenation

• Delay operator

• Bitwise AND

Which keyword is used to define a sequence of events?

• event

• sequence

• property

• assert

Which of the following is used to monitor coverage of sequences?

• covergroup

• cover

• assert

• coverpoint

What does |-> denote in a property definition?

• Implication

• Equality

• Delay

• Conjunction

Which assertion type is evaluated in procedural code blocks?

• Immediate

• Concurrent

• Temporal

• Static