Understanding Pipelining and Memory Models

What is pipelining in the context of computer architecture?

• A technique where multiple processors execute the same instruction simultaneously

• A technique that breaks a task into stages so that multiple tasks can be processed simultaneously at different stages

• A method of storing data in a distributed memory system

• A process of synchronizing shared memory across multiple processors

What is a pipeline hazard?

• A physical fault in the pipeline hardware

• A situation that prevents the next instruction in the pipeline from executing during its designated clock cycle

• An overflow error caused by too many pipeline stages

• A memory leak in distributed shared memory systems

Which of the following is NOT a type of pipeline hazard?

• Structural hazard

• Data hazard

• Control hazard

• Memory hazard

In a symmetric shared memory (SMP) system, how do all processors access memory?

• Each processor has its own private memory with no sharing

• All processors share a single memory space with equal access time

• Processors access memory through a distributed network with variable latency

• Memory is divided into segments, each exclusively owned by one processor

What does pipeline throughput measure?

• The total number of pipeline stages

• The time taken to complete a single task in the pipeline

• The number of tasks completed per unit time

• The number of hazards encountered per pipeline cycle

Pipeline efficiency is defined as:

In a distributed shared memory (DSM) system, what happens when a processor accesses memory that is physically located on a remote node?

• The access is denied and an error is returned

• The access is transparent to the programmer but incurs higher latency than local memory access

• The data is permanently moved to the local node's memory

• The access time is identical to accessing local memory

A data hazard in a pipeline occurs when:

• Two instructions require the same hardware resource simultaneously

• A branch instruction causes uncertainty about which instruction to fetch next

• An instruction depends on the result of a previous instruction that has not yet completed

• The pipeline runs out of instructions to process