Free Printable VLSI Design Module-1

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VLSI Design Module-1

Total questions: 35

Worksheet time: 35mins

Name

Class

Date

What is Moore's law

Number of transistors increases every 12 months

Number of transistors doubles every 18 months

Number of transistors increases every 12 months

Number of transistors triples every 18 months

How many terminals are there for a MOSFET

Two

Three

Four

Five

What should be the condition for Vg so that the MOSFET operates in depletion region

Vg=0

Vg>0

0<Vg<Vt

Vg>Vt

In which region of MOSFET, Ids is linearly dependent on Vds

Active

Triode

Cutoff

Saturation

Which of the following is the condition for linear region of a MOSFET (select all that apply)

Vds=0

Vds>Vt

0<Vds<Vgs-Vt

Vds>Vgs-Vt

What should be value of gate voltage to turn on the nMOS

-1

None of the above

What should be the value of gate voltage to turn on pMOS

-1

None of the above

With what velocity the charge carriers in a channel will be moving between source and drain

v= $\mu$ E

v= $\lambda$ E

v=d/t

v=E/t

VLSI technology uses ________ to form integrated circuit

transistors

switches

diodes

buffers

10.

Small scale Integration circuits have

10 gates

1000 gates

10000 gates

Unlimited gates

11.

______ architecture is used to design VLSI

System on Device

System on Chip

System on a Circuit

None of the above

12.

MOS transistors consists of

semiconductor layer

metal layer

layer of silicon-di-oxide

all of the above

13.

In MOS transistors, _____ is used for their gate

Metal

Silicon di Oxide

Source/Drain

Polysilicon

14.

Electrical charge flows from

Source to drain

Drain to Source

Source to gate

gate to drain

15.

Source in nMOS transistors is doped with ______ material

p-type

n-type

both n and p-type

Neither n or p-type

16.

Which expression is true when driving a capacitive output load

charging time < discharging time

charging time > discharging time

charging time = discharging time

charging time and discharging time are not related

17.

What are the advantages of BiCMOS?

higher gain

high frequency characteristics

better noise characteristics

all of the mentioned

18.

BiCMOS can be used in

amplifyig circuit

driver circuits

divider circuit

multiplier circuit

19.

During the fabrication process the photoresist layer is exposed to

visible light

ultraviolet light

infra red light

LED

20.

SIlicon-di-oxide is a good insulator

true

false

21.

If the n-MOS and p-MOS of the CMOS inverters are interchanged the output is measured at:

Source of the both transistor

Drains of the both transistor

Drain of n-MOS and source of p-MOS

Source of n-MOS and drain of p-MOS

22.

What will be the effect on output voltage if the positions of n-MOS and p-MOS in CMOS inverter circuit are exchanged?

Output is same

Output is reversed

Output is always high

Output is always low

23.

Which is true for nMOS pass transistors

Passes both 0 and 1 well

Passes 0 well and 1 poorly

Passes 1 well and 0 poorly

Passes both 0 and 1 poorly

24.

What is NOT the correct way of connecting the nMOS transistors in cascade

Source of one device is connected to Source of another

Source of one device is connected to Gate of another

25.

When the input of the CMOS inverter is equal to Inverter Threshold Voltage Vth, the transistors are operating in:

N-MOS is cutoff, p-MOS is in Saturation

P-MOS is cutoff, n-MOS is in Saturation

Both the transistors are in linear region

Both the transistors are in saturation region

26.

The switching threshold voltage VTH for an ideal inverter is equal to:

(VDD-VOL)/2

VDD

(VDD)/2

27.

P-well is created on

p subtrate

n substrate

p & n substrate

none of the mentioned

28.

In high noise margin (NM_H), the difference in magnitude between the maximum HIGH output voltage of driving gate and the maximum HIGH voltage is recognized by the _________gate.

Driving

Recieving

Both a and b

None of the above

29.

When is the inverter called as HI Skewed

When $\beta_p$ = $\beta_n$

When $\beta_p$ < $\beta_n$

When $\beta_p$ > $\beta_n$

None of the above

30.

What is the expected output of Tristate inverter if the input is A and En=1

$\ \overline{A}$

31.

nMOS transistors attempting to pass '1' will never pull the source above

VDD

Vtn

VDD-Vtn

32.

Transmission gates can be considered as

Voltage controlled register

Current controlled register

Voltage controlled current

Current controlled current

33.

$NM_H$ = $V_{OH}$ - $V_{IH}$ The term $V_{IH}$ represents

Minimum HIGH input voltage

Maximum LOW input voltage

Minimum HIGH output voltage

Maximum LOW output voltage

34.

In CMOS inverter, output voltage drops to 0 when

0<Vin<Vtn

Vtn<Vin<VDD/2

Vin=VDD/2

Vin>(VDD/2)-|Vt|

35.

Which of the following is true about Junction leakage current

Decreases with T

Increases with T

Not affected with any change in T

Doubles with increase in T

Reset

VLSI Design Module-1

Total questions: 35

Worksheet time: 35mins

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