WorksheetsDIGITAL-FlipFlops
Total questions: 20
Worksheet time: 10mins
The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
d) Current state
The flip-flops which has not any invalid states are _____________
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T
What does the triangle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Edge triggered
c) Both Level enabled & Edge triggered
d) Level triggered
On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
What does the circle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered
What would be the characteristic equation of SR latch corresponding to the K-map schematic shown below?
a. S + RQn
b. S + R'Qn
c. S' + RQn
d. S' + R'Q'n
Which is the prohibited state/ condition in S-R latch and needs to be avoided due to unpredictable nature of output?
a. S = R = 0
b. S = 0, R = 1
c. S = 1, R = 0
d. S = R = 1
Sequential circuit contains
a) No memory element
b) Atleast one memory element
c) All inputs applied simultaneously
d) None of the above
T Flip flop is used as
Transfer data circuit
Toggle switch
Time delay switch
None of the above
On a master-slave flip-flop, when is the master enabled?
A.when the gate is LOW
B.when the gate is HIGH
C.both of the above
D.neither of the above
A counter circuit is usually constructed of ____________
a) A number of latches connected in cascade form
b) A number of NAND gates connected in cascade form
c) A number of flip-flops connected in cascade
d) A number of NOR gates connected in cascade form
The advantage of a J-K flip-flop over an S-R FF is that ________.
A.it has fewer gates
B.it has only one output
C.it has no invalid states
D.it does not require a clock input
----------- is the amount of time that an input signal must be stable before clock ticks to avoid possible metastability is
propagation delay
setup time
hold time
none of the above
How many natural states will there be in a 4-bit synchronous counter?
a) 4
b) 8
c) 16
d) 32
Asynchronous counter is otherwise known as ----------
Parallel counter
Ripple counter
synchronous counter
None of the above
in ----------- counter output of the last flip flop is connected to the first flip flop
Ripple counter
Ring counter
Johnson counter
Parallel counter
If ‘n’ is the number of flip flop used in Johnson counter, then the total number of states used is
2^n
n
2n
n^2
Another name for synchronous counter is
Ripple counter
Asynchronous counter
Parallel counter
All of the above
Following flip flop is used to eliminate race around problem
SR Flip flop
JK Flip flop
Master Slave Flip flop
D Flip flop
