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VLSI_Q1

Total questions: 10

Worksheet time: 5mins

Name
Class
Date
1.

_______ is the photoresist which is initially soluble and becomes insoluble when exposed to UV light

a)

Positive photo resist

b)

Negative photo resist

c)

chrome

d)

reticle

2.

In fabrication ___________is the process of building wires to connect the devices.

a)

Metallization

b)

Sputtering

c)

Routing

d)

Passivation

3.

If β = [(W/L)P/(W/L)N] is increased, which of the following statement is true

a)

TpHL>TpLH

b)

TpHL<TpLH

c)

TpHL=TpLH

d)

No change in delay

4.

For a static CMOS, the output is high, then the state of the NMOS and PMOS are as follows

a)

NMOS off and PMOS linear

b)

NMOS off and PMOS non-linear

c)

NMOS on and PMOS non-linear

d)

NMOS on and PMOS linear

5.

For a static CMOS inverter, when the aspect ratio of the pull down network is increased,

then which of the following statement is true

a)

TpHL increases

b)

NML increases

c)

NMH increases

d)

TPLH increases

6.

For a bulk MOSFET with aspect ratio of W/L and a depletion width of XD the analytical expression for gate-to-drain overlap capacitance (Cgd) is____

a)

Cgd = CoxXDWL

b)

Cgd = CoxXDW/2

c)

Cgd = 2CoxXDWL

d)

Cgd = 2CoxWXD

7.

In stick diagram, n and p transistors are separated by using ____________

a)

Diffusion

b)

Demarcation line

c)

N well

d)

PR boundary

8.

AOI realization is suitable for realizing functions in _____ form

a)

sop

b)

Pos

c)

CVSL

d)

Pseudo NMOS

9.

The static PD for CMOS logic is maximum when input is at

a)

vdd

b)

vdd/2

c)

vdd/4

d)

2vdd

10.

------------------- can pass a logic 1 perfectly, but cannot pass a logic 0 perfectly

a)

nmos

b)

Transmission gate

c)

pmos

d)

keepers