The DMA controller has _______ channels

DMA Controller request for control of busses to microprocessor through _____ pin

The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert the _____

Each channel of DMA Controller can transfer data maximum up to _____

Each channel of DMA Controller can perform

These are the four individual channel DMA request inputs, which are used by the peripheral devices for using DMA services

These are the active-low DMA acknowledge lines, which updates the requesting peripheral about the status of their request by the CPU.

It generates '______ signal to the peripheral device that 128 bytes have been transferred.

_______ is designed by Intel to transfer data at the fastest rate. It allows the device to transfer the data directly to/from memory without any interference of the CPU.

_____ when enabled, permits block chaining operations, without immediate software intervention between blocks. In this mode, channel 2 parameters (DMA starting address, terminal count and DMA transfer mode) are initialized as usual for the first data block.

If the _______ is set, a channel is disabled after the terminal count (TC) output goes high,

It generates '______ signal to the peripheral device that 128 bytes have been transferred.