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WorksheetsMPMC 8086 system bus architecture(unit 2)
Total questions: 20
Worksheet time: 10mins
8086 Microprocessor supports _______ modes of operation.
2
3
4
None of these
Which of the following is not a Features of 8086?
It uses two stages of pipelining
It is available in 3 versions based on the frequency of operation
Fetch stage can prefetch up to 6 bytes of instructions
It has 512 vectored interrupts.
8086 can access up to?
4KB
1GB
1MB
64KB
ALE stands for
Address Low Enable
Advanced Latch Enable
Address Level Enable
Address Latch Enable
Which method bypasses CPU for certain types of data transfer?
Hardware Interrupts
Software interrupts
I/O interface
Direct Memory Access
Microprocessor sends a _________________ signal on RD to do the read operation
High
Low
high impedence
None of these
DEN stands for
Data Enable
Direct Enable
Device Enable
None of these
8259 is
PIC controller
Bus Controller
Clock generator
None of these
8288 came into picture in
min mode
max mode
both modes
None of these
Which of the following is a bus arbitration method in loosely coupled configuration?
Daisy Chaining
Polling
Independent Requests
All of these
8284 is
PIC controller
Bus controller
clock generstor
None of these
READY signal is used to
increase the number of interrupts
synchronize with slow devices
perform DMA
None of these
HOLD and HLDA are used to
perform DMA
access bus
generate delays
All the above
1 Machine cycle= ___________ T states
2
4
5
3
Crystal frequency is divided by 3 to get
6MHz clock frequency
33% duty cycle clock
because there are 3 processors
all of the above
Which of the following in a false statement?
Coprocessor is interfaced in max mode
Coprocessor is interfaced in min mode
I/O interface can be done in both modes
supports pipelining
Pentium supports
2 stage pipeline
3 stage pipeline
4 stage pipeline
5 stage pipeline
2 way superscalar architecture is presented in
80186
80386
80486
Pentium
How many levels of protection in 80486?
4
3
2
6
The Paging unit converts
logical address to physical address
logical address to linear address
linear address to physical address
physical address to logical address
