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WorksheetsELECS 40
Total questions: 50
Worksheet time: 25mins
Junction Field Effect Transistors (JFET) contain how many diodes?
4
3
2
1
When an input delta of 2 V produces a transconductance of 1.5 mS, what is the drain current delta?
666 mA
3 mA
0.75 mA
0.5 mA
When not in use, MOSFET pins are kept at the same potential through the use of:
shipping foil
nonconductive foam
conductive foam
a wrist strap
D-MOSFETs are sometimes used in series to construct a cascode high-frequency amplifier to overcome the loss of:
low output impedance
capacitive reactance
high input impedance
inductive reactance
A "U" shaped, opposite-polarity material built near a JFET-channel center is called the:
gate
block
drain
heat sink
When testing an n-channel D-MOSFET, resistance G to D = ∞, resistance G to S = ∞, resistance D to SS = ∞ and 500Ω, depending on the polarity of the ohmmeter, and resistance D to S = 500Ω. What is wrong?
short D to S
open G to D
open D to SS
nothing
In the constant-current region, how will the IDS change in an n-channel JFET?
As VGS decreases ID decreases.
As VGS increases ID increases.
As VGS decreases ID remains constant.
s VGS increases ID remains constant.
A MOSFET has how many terminals?
2 or 3
3
4
3 or 4
IDSS can be defined as:
the minimum possible drain current
the maximum possible current with VGS held at –4 V
the maximum possible current with VGS held at 0 V
the maximum drain current with the source shorted
What is the input impedance of a common-gate configured JFET?
very low
low
high
very high
JFET terminal "legs" are connections to the drain, the gate, and the:
channel
source
substrate
cathode
A very simple bias for a D-MOSFET is called:
self biasing
gate biasing
zero biasing
voltage-divider biasing
With the E-MOSFET, when gate input voltage is zero, drain current is:
at saturation
zero
IDSS
widening the channel
With a 30-volt VDD, and an 8-kilohm drain resistor, what is the E-MOSFET Q point voltage, with ID = 3 mA?
6 V
10 V
24 V
30 V
When an input signal reduces the channel size, the process is called:
enhancement
substrate connecting
gate charge
depletion
Which JFET configuration would connect a high-resistance signal source to a low-resistance load?
source follower
common-source
common-drain
common-gate
How will electrons flow through a p-channel JFET?
from source to drain
from source to gate
from drain to gate
from drain to source
When VGS = 0 V, a JFET is:
saturated
an analog device
an open switch
cut off
When applied input voltage varies the resistance of a channel, the result is called:
saturization
polarization
cutoff
field effect
When is a vertical channel E-MOSFET used?
for high frequencies
for high voltages
for high currents
for high resistances
When the JFET is no longer able to control the current, this point is called the:
breakdown region
depletion region
saturation point
pinch-off region
With a JFET, a ratio of output current change against an input voltage change is called:
transconductance
siemens
resistivity
gain
Which type of JFET bias requires a negative supply voltage?
feedback
source
gate
voltage divider
How will a D-MOSFET input impedance change with signal frequency?
As frequency increases input impedance increases.
As frequency increases input impedance is constant.
As frequency decreases input impedance increases.
As frequency decreases input impedance is constant.
The type of bias most often used with E-MOSFET circuits is:
constant current
drain-feedback
voltage-divider
zero biasing
The transconductance curve of a JFET is a graph of:
IS versus VDS
IC versus VCE
ID versus VGS
ID × RDS
The common-source JFET amplifier has:
a very high input impedance and a relatively low voltage gain
a high input impedance and a very high voltage gain
a high input impedance and a voltage gain less than 1
no voltage gain
Using voltage-divider biasing, what is the voltage at the gate VGS?
5.2 V
4.2 V
3.2 V
2.2 V
The overall input capacitance of a dual-gate D-MOSFET is lower because the devices are usually connected:
in parallel
with separate insulation
with separate inputs
in series
What is the transconductance of an FET when Δ ID = 1 mA and Δ VGS = 1 V?
1 kS
1 mS
1 kΩ
1 mΩ
Which component is considered to be an "OFF" device?
transistor
JFET
D-MOSFET
E-MOSFET
In an n-channel JFET, what will happen at the pinch-off voltage?
the value of VDS at which further increases in VDS will cause no further increase in ID
the value of VGS at which further decreases in VGS will cause no further increases in ID
the value of VDG at which further decreases in VDG will cause no further increases in ID
the value of VDS at which further increases in VGS will cause no further increases in ID
The two basic types of signals are analog and:
digilog
digital
vetilog
sine wave
Which of the following characterizes an analog quantity?
Discrete levels represent changes in a quantity.
Its values follow a logarithmic response curve.
It can be described with a finite number of steps.
It has a continuous set of values over a given range.
ASCII stands for:
American Serial Communication Interface
Additive Signal Coupling Interface
American Standard Code for Information Interchange
none of the above
Which type of signal is represented by discrete values?
noisy signal
nonlinear
analog
digital
A data conversion system may be used to interface a digital computer system to:
an analog output device
a digital output device
an analog input device
a digital printer
The output will be a LOW for any case when one or more inputs are zero in a(n):
OR gate
NOT gate
AND gate
NAND gate
If a signal passing through a gate is inhibited by sending a low into one of the inputs, and the output is HIGH, the gate is a(n):
AND
NAND
NOR
OR
A single transistor can be used to build which of the following digital logic gates?
AND gates
OR gates
NOT gates
NAND gates
The logic gate that will have HIGH or "1" at its output when any one of its inputs is HIGH is a(n):
OR gate
AND gate
NOR gate
NOT gate
How many NAND circuits are contained in a 7400 NAND IC?
1
2
4
8
Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
OR gates only
AND gates and NOT gates
AND gates, OR gates, and NOT gates
OR gates and NOT gates
How many truth table entries are necessary for a four-input circuit?
4
8
12
16
A NAND gate has:
LOW inputs and a LOW output
HIGH inputs and a HIGH output
LOW inputs and a HIGH output
None of the these
The basic logic gate whose output is the complement of the input is the:
OR gate
AND gate
INVERTER gate
comparator
What input values will cause an AND logic gate to produce a HIGH output?
At least one input is HIGH.
At least one input is LOW.
All inputs are HIGH.
All inputs are LOW.
A digital logic device used as a buffer should have what input/output characteristics?
high input impedance and high output impedance
low input impedance and high output impedance
low input impedance and low output impedance
high input impedance and low output impedance
What is the standard TTL noise margin?
5.0 V
0.2 V
0.8 V
0.4 V
When an IC has two rows of parallel connecting pins, the device is referred to as:
a QFP
a DIP
a phase splitter
CMOS
