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WorksheetsBasic and Advanced Verilog HDL module
Total questions: 46
Worksheet time: 35mins
Which of the following is standardised as IEEE 1364?
C
C++
FORTRAN
Verilog
Who developed the Verilog?
Moorby
Russell and Ritchie
Moorby and Thomson
Thomas
Which of the following is a Verilog version 1.0?
IEEE standard 1394-1995
IEEE standard 1364-1995
IEEE standard 1394-2001
IEEE standard 1364-2001
The default value for reg data type is
0
x
1
z
What are the possible values of == operator
0
x
z
1
@posedge means
Transition from 0 to 1, x or z
Transition from x to 1
Transition from z to 1, x
Transition from 1 to 0
The wait statement is
level sensitive
edge sensitive
both
none
To suspend a simulation, you can use this system task command.
$end
$finish
$stop
$close
In continuous assignment statement LHS can be
Vector net
Scalar net
Concatenation of both
all of the above
To trigger an event, we can use the following operator.
---->
==
@
=>
In non-blocking assignment, the compiler
Evaluates all RHS for the current time unit and assign to LHS at the end of time unit
Evaluates all RHS for the current time unit and assign to LHS at the current time
Both of the above options are correct, depending on the specific case
None of the options are correct
Netlist is a ______ representation of a circuit.
graphic
text‐based
handwritten
pictorial
RTL stands for _____________.
a.
c.
resistor‐transfer logic
register‐transistor logic
register‐transfer logic
none of these
Verilog HDL originated at
AT&T Bell laboratories
Defense Advanced Research Projects Agency(DARPA)
Gateway Design Automation
Institute of Electrical and Electronics Engineers(IEEE)
Which is legal negative number
4'd-3
6'-d3
-6d'3
None
What is the time period of clock #10 clock = ~clock
10
20
5
None
#40 $finish indicates
end of simulation time
end of simulation at 40 time units
suspend simulation at 40 time units
None
What is the width of time register
16 bit
32 bit
64 bit
128 bit
%g or %G displays
Real numbers in decimal or scientific notation
Real numbers in decimal or scientific notation whichever shorter
Real numbers in scientific format
Real numbers in decimal format
Parameter value can be overridden at module instance by
`define
`include
`ifdef
`timescale
If x=4'b1100 then x<<2 is
4'b1000
4'b0000
4'b0011
4'b0110
If x=4'b1100 then &x equals
1'b0
1'b1
4'b1100
None
If A=4'b1010 and B=4'b1100 then A&B
4'b0000
4'b1000
1'b1
1'b0
If A=1'b1,B=2'b01,C=2'b00 then y= {A,B[0],C[1]} equals
3'b110
3'b100
3'b101
1'b0
If A=1'b1,B=2'b01,C=2'b00 y={4{A},2{B},C} equals
10'b1111010100
9'b111101010
8'b11110100
None
casex treats
0 as don't care
x as don't care
z as don't care
Both x and z as don't care
<= is used in
Blocking
Non Blocking
Both
None
Asynchronous reset is
Clock dependent
Clock independent
Either
None
Which construct is used to execute loop fixed number of times
repeat
while
forever
None
Random number is generated by
$random
$rand
$strobe
None
Setup time is
Minimum time the data must arrive before active clock edge
Maximum time the data must arrive before active clock edge
Minimum time the data cannot change after active clock edge
None
Arrays are not allowed for
integer
register
time
real
Which directive is used to include entire content of Verilog source Into another file
'include
'ifdef
'ifndef
None
All ports by default are
reg
inout
wires
Should be defined
inout ports must always be
reg
net
trireg
none
The left hand side of procedural continuous assignment can be
Register or concatenation of registers
Net or concatenation of nets
Can be both registers or nets
Array of registers
For the segment given below choose the correct answer
bufif0 #(5,6,7) c1(out,in,cntrl)
5=rise 6=turnoff 7=fall
5=fall 6=rise 7=turnoff
5=rise 6=fall 7=turnoff
5=turnoff 6=rise 7=fall
Which of the following is true about always statement
There may be exactly one always block in a design.
There may be exactly one always block in a module
Execution of an always block occurs exactly once per simulation run
An always block may be used to generate a periodic signal
In UDP (user defined premitives)
Multiple input and one output is permitted
One input and multiple output is permitted
Multiple input and multiple output is permitted
One input and one output is permitted
For the below code segment given below
always @(posedge clk)
a=b;
always @(posedge clk)
b=a;
Values of a and b are swapped
Values of a and b cannot be swapped
Values of a and b can be swapped depending on simulator
Can't determine
Clock skew is the phenomenon of
Synchronous circuit
Asynchronous circuit
Both
None
Cycle based simulation is useful for
Synchronous circuit
Asynchronous circuit
Both
None
For tri0 what is the value when nothing is driving
1
0
x
z
Which is object oriented programming
VHDL
Verilog
System Verilog
none
wand differs from wor in the way
wand forced to one if any driver to it is zero while wor forced to zero if any driver to it is zero
wand forced to zero if any driver to it is zero while wor forced to one if any driver to it is one
wand forced to zero if any driver to it is one while wor forced to one if any driver to it is zero
wand forced to one if any driver to it is one while wor forced to zero if any driver to it is zero
If there is mismatch in connecting wire such as
Y1[7:0] = Y2[15:0]
The end result is Y1[7:0]=Y2[15:0]
The end result is Y1[15:0]=Y2[7:0]
The end result is Y1[7:0]=Y2[7:0]
Can't determine
