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WorksheetsIT Hardware Software
Total questions: 54
Worksheet time: 28mins
What are the drawbacks of sequential interrupt processing?
Does not allow to handle priority interrupts
Does not give priority to time-critical needs
Works with first come first serve basis
Handle interrupts one after another
Choose the answer which is not part of the 6 computer level hierarchy we mentioned during the class?
Manufacturer
User
Assembly
Digital Logic
Which one of them is lowest level of computer level hierarchy?
Digital Logic
Machine
User
Control
Interrupt handler routine is a part of...
operating system
hardware
processor
I/O module
What is control bus responsible for?
Sending control signals read, write or opcodes
Sending data
Sending address
Connection between 2 devices
What are the possible approaches to deal with multiple interrupts?
Sequential, nested
Sequential, parallel
Nested, parallel
Parallel, perpendicular
16 bit long system, 4 bits for opcode. Instruction 4927 Hex.
What is the next memlory adress to execute data?
927
27
7
492
Which of the following is not part of main structural element of the computer?
Processor
Memory
System bus
Motherboard
Which module is responsible for exchange of daa between input output module and processor?
IO BR
MBR
MAR
IO AR
It takes 277.78 nano seconds to complete 1 cycle. What is clock rateof CPU?
3.6 MHz
4.2 Ghz
4.1 Mhz
2 Mhz
An increase in clock rate means that individual operations are executed...
more rapidly
the same
slower
with the little change
Which is example of program interrupt?
generated by timer
generated by failure (power, memory)
division by 0
generated by system
What is primary design goal of interrupts?
improve IO processes
improve processor utilization
improve the lifetyme of a computer
improve the brithness of screen
What is function of MAR?
Specifies the adress in memory forread or write
Specifies a particular bus
Specifies a memory type
Executing instruction
Which of the following is the correct execution cycle order?
start, fetch, execute, halt
fetch, execute, start, halt
halt, start, execute, fetch
fetch, execute
A _______ is a core designed to perform parallel operations on graphics data
GPU
MIC
ALU
PGD
Which one is one of the approaches to deal with multiple interrupts?
Sequential interrupt processing
Horizontal interrupt processing
Parallel interrupt processing
Vertical interrupt processing
What are the drowbacks of sequential interupt processing?
Does not allow to handle priority interrupts
Does not give priority to time critical needs
Works with first come first serve basis
Handle interrupts oen after another
Which is not a basic component of computer?
Processor
Memory
Bus
GPU
16 bits long system, 4 bits for opcode,. Instruction: 4927 Hex. What is next instruction?
0100
1111
927
4927
Clock rate of computer is 300KHz. How long it takes to complete 1 cycle?
3.33 nanoseconds
3.33 microseconds
4.44 milliseconds
3.33 seconds
Interrupt handler routine is a part of
operating system
hardware
processor
IO module
IO address register responsible for
specyfying a particular IO device
exchanging data between IO module and processor
specifying memory address
controlling execution process
Planning to put 128 instructions in system, each 16 bits long. How many addresses can be direcly pointed from our instruction?
2^9
2^10
2^6
2^16
Which is not part of main structural part of computer?
Processor
Memory
System bus
Motherboard
Not part of CPU
PC
RAM
Screen
Video graphic card
Primary design goal of interrupt
improve IO processes
improve processor utilization
improve lifetyme of computer
improve brightness of screen
Types of interrupts
program, timer,io, hardware failure
cpu, java, power bi, c++
error, exception, cpu, monitor
none of above
Which is mre specific to user level of the 6 computer level hierarchy?
program execution and user interface (UI) level
writing programs in high level languages
controlling execution process on the system
protecting system resources
Which of them is not true for R7=R7+12
ADD R7, R7, #12
ADD R7, R7, #0xC
ADD R7, R7, 0b1100
ADD R7, R7, 0bxC
Which of them is true? SUB R3 R4 R5
SUB is mnemonic
R3 source is source operand
R3 and R4 are source operands
R5 and R4 are destination operands
What is spacial locality?
tendency executing the instruction or accesing data location sequentially
tendency accessing the instruction or data locations that have been visited
geographical coordinates of CPU manufacturers
iterative nature of process execution
Temporal locality principle
tendency accessing the instruction or data locations that have been visited recently
the temporary storage of data
accessing instruction sequentially
accessing data sequentially
What does exploiting the principle of locality solve?
providing memory cycle times comparable to processor cycle times
increases memory cycle time
provides more space in memory
provides connection between the processr and io module
Where does virtual memory locate?
hard disk
RAM
ROM
Processor
What does exploiting the principle of locality solve?
provides memory cycle time compartable to processor cycle times
increase memory cycle time
provides more space in memory
provides connection between the processor and io module
What is temproral locality principle?
tendency accesing the instructions or data locations that have been visited recently
temporary storage of data
accessing instructions sequentically
accessing data sequentically
Which condition flag may be effecred instruction below?
SUBS R2 R3 R7; R2 = R3
N
Z
C
All of them
Spacial locality is
tendency accesing the instructions or data locations that have been visited sequentially
tendency accesing the instructions or data locations that have been visited recently
geographical coordinates of cpu manufacturers
iterative nature of process execution
Correct order based on efficiency? (first lead efficient, last least efficient)
programmed io, interrupt driven io, dma
dma, interrupt driven io, programmed io
programmed io, dma, interrupt driven io
interrupt driven io, dma, programmed io
What is assembly code instruction below?
Move register3 ro register 8.
MOV R8, R3
MOV R3, R8
MOVE R3, R8
MOVE R8, R3
True statements about instruction sets
ARM is architecture
RISC computers can perform complex instructions
Intel X86 is a CISC architecture
CISC computers can perform complex instructions with multiple simple instructions
In which case second instruction will be executed
CMP R4 R5
ADDEQ R1 R2 R3
R4 = R5
R2 = R1
R5 > R4
R2 = R3
Memory cycle time is
time required to write one word to memory
time required to execute instruction
time required to read one word from registers
time required to write one word to IO data buffer
Level 1: capacity 500 bytes cost per bit is 30
Level 1: capacity 2500 bytes cost per bit is 10
Avg cost per bit?
40/3
300/127
500
125
Which is not flag of ARM instructions?
M
Z
C
V
What does exploiting the principle of locality solve?
provides memory time cycle times comparatble to processor cycle times
increases memory cycle time
provides more space in memory
provides connection between the processor and io module
Purpose of LRU algorithm in cache?
an effective strategy to replace a block that has been read into the memory
an effective strategy to write memory back to original place
find data to read into cache
mechanism that hardware uses to boot the system
Choose all characteristics as you move down the memory hierarchy
increasing capacity
decreasing cost per bit
increasing access time
decreasing frequency of access to the memory by the processor
Not computer architecture
Assembly
ARM
x86
Power PC
Level 1: capacity 500 bytes. Access time 0.2ms
Level 1: capacity 5000 bytes. Access time 1ms
Suppose 98% of memory accesses are found in level 1. Suppose if data in level 2 needs to be transeffered to level 1, then accessed by processor. Find avg time needed to access a byte?
0.22 ms
0.4 s
1.1 Bs
1.1 Bms
Tradeoffs among characteristics of memory
capacity, access time, design
cost, capacity, access time
value, capacity, hardware
software, cost, hardware
Not true...
Operands can be stored in registers or memory, or they may be contants stored in instruction itself
Operands stored as constants or in registers are accesses slower, but they hold only a small amount of data
Additional data must be accesses from memory , whch is large but slow
ARM is a 32 bit architecture
True about CMP instruction
It substracts tthe 2nd source operand from the 1st and setd the condition flags based on the result
If numbers are equal the result is zero
If numbers are equal to Z flag is et
number cannot be negative
