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Total questions: 101
Worksheet time: 51mins
Latches are used to
store single bit
store 2 bits
store 1 byte
none of the above
SR latches use
NAND gates
NOR gates
AND gates
OR gates
When S=1 and R=0, what will happen
Q=0 (reset)
q'=1
Q=1 (set)
Q=no change (latch)
invalid state q' = Q
When S=0 and R=0, what will happen
Q=0 (reset)
q'=1
Q=1 (set)
Q=no change (latch)
invalid state q' = Q
When S=0 and R=1, what will happen
Q=0 (reset)
q'=1
Q=1 (set)
Q=no change (latch)
invalid state q' = Q
When s'=1 and r'=1, what will happen
Q=0 (reset)
q'=1
Q=1 (set)
Q=no change (latch)
invalid state q' = Q
When s'=0 and r'=1, what will happen
Q=0 (reset)
q'=1
Q=1 (set)
Q=no change (latch)
invalid state q' = Q
When s'=1 and r'=0, what will happen
Q=0 (reset)
q'=1
Q=1 (set)
Q=no change (latch)
invalid state q' = Q
When s'=0 and r'=0, what will happen
Q=0 (reset)
q'=1
Q=1 (set)
Q=no change (latch)
invalid state q' = Q
If we create a D latch from either a SR or a s'r' latch, when D=1 and E=1 what will happen
D=0 (reset)
d'=1
D=1 (set)
no change in D (latch)
invalid state d' = D
If we create a D latch from either a SR or a s'r' latch, when D=1 and E=0 what will happen
D=0 (reset)
d'=1
D=1 (set)
no change in D (latch)
invalid state d' = D
If we create a D latch from either a SR or a s'r' latch, when D=0 and E=1 what will happen
D=0 (reset)
d'=1
D=1 (set)
no change in D (latch)
invalid state d' = D
If we create a D latch from either a SR or a s'r' latch, when D=0 and E=0 what will happen
D=0 (reset)
d'=1
D=1 (set)
no change in D (latch)
invalid state d' = D
Latch is a
combinational circuit
analog circuit
sequential circuit
none of the above
In SR Flip Flops, given the inputs S = 0, R =0, and Present state Qn = 0. Find the Next State Qn+1 .
01
1
Dont care
0
In SR Flip flop, given the inputs S=0, R=1, and Present state Qn=1, Then next state Qn+1 =
0
1
Dont care
In SR Flip Flops, given the inputs S=1, R=1, and present state Qn= 1, then
1
0
Indeterminant
In JK Flip Flops, given the inputs J=1, K=1, and present state Qn= 1, then
1
0
Indeterminant
In JK Flip Flops, given the inputs J=1, K=0, and present state Qn= 1, then
1
0
Indeterminant
In D Flip Flops, given the inputs D=1,present state Qn= 1, then
1
0
Indeterminant
In T Flip Flops, given the inputs T=1,present state Qn= 1, then
1
0
Indeterminant
In T Flip Flops, given the inputs T=0,present state Qn= 1, then
1
0
Indeterminant
Given SR excitation table with present state Qn=0, next state Qn+1=1, then find the inputs
S=0 , R = 1
S=1 , R= 0
S=0 , R = x
S=x , R= 0
Given JK excitation table with inputs Qn=1, Qn+1=0, then find the inputs J and K
J=x , K = 1
J=1 , K = x
J=0 , K= x
J=x ,K = 0
Given D excitation table with inputs Qn=0,Qn+1=1 then find the input D
1
0
dont care
Given T excitation table with inputs Qn=1,Qn+1=1 then find the inputs
1
0
dont care
In D Flip Flops, given the inputs D=0,present state Qn= 1, then
1
0
Indeterminant
In SR flip flops , when the given inputs are S=1 and R =1 , then next state will be
No change
Reset
Indeterminant
Toggle
In JK flip flops , when the given inputs are J=1 and K =1 , then next state will
Not change
Reset
Indeterminant
Toggle
In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
The flip-flops which has not any invalid states are _____________
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, T
Sequential circuit contains
a) No memory element
b) Atleast one memory element
c) All inputs applied simultaneously
T Flip flop is used as
Transfer data circuit
Toggle switch
Time delay switch
The advantage of a J-K flip-flop over an S-R FF is that ________.
A.it does not require a clock input
B.it has only one output
C.it has no invalid states
Following flip flop is used to eliminate race around problem
SR Flip flop
JK Flip flop
Master Slave Flip flop
Number of inputs for D flip flop
3
2
1
In a J-K flip-flop, if J=K the resulting flip-flop is referred to as
D flip-flop
T flip-flop
S-K flip-flop
The flip-flop is only activated by _____________
Positive edge trigger
Negative edge trigger
Either positive or Negative edge trigger
The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
Combinational Circuits
Sequential Circuits
None of the above
Clock
Q = D'
Q
What type of register would shift a complete binary number in one bit at a time and shift all the stored bits out one bit at a time?
PISO
SISO
PIPO
SIPO
…………………….. Logic circuits depends upon both the input as well as the previous output of the circuit
(a)
Latches and Flip flops are the examples of …………………. Logic circuits
Combinational
Sequential
Feedback path, and memory elements are the parts of sequential circuits say True or False
True
False
Sequential circuits are faster than combinational circuit say True or False
True
False
In S-R Latch; When Q is HIGH, the latch is in ………….. State
(a)
In S-R Latch; When Q is LOW, the latch is in ………….. State
(a)
In synchronous Sequential circuits; It has a common …………….. Signal for controlling the changes of the state of the circuit.
(a)
The interval after the clock where the data must be held stable
Setup time
Hold time
The flip-flops which has not any invalid states are _____________
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, T
Bistable circuit can be used to store information of
one bit
two bits
three bits
four bits
SR Latch consists of
2 inputs
3 inputs
1 inputs
4 inputs
Asynchronous sequential logic circuit does not depend on
inputs
inputs and outputs
clock
outputs
If each of the possibilities of a race eventually leads to the same stable state, then the race is said to be
Non critical race
critical race
cycle
hazard
For the asynchronous sequential circuit shown in Fig.1, choose the appropriate next state equations
Y1=xy1+x’y2
Y2=xy’+x’y2
Y1=xy1+xy2
Y2=x + x’y2
Y1=x’y1+x’y2
Y2=x’y’+x’y2
The Fig 3 shown below illustrates
Races
Dynamic hazard
Static-1-hazard
Static-0-hazard
In the following PLA structure, which output implements the logic function ABCD?
X
Y
Z
X AND Y
Find the number of feedback loop shown in Fig
1
2
3
4
The present-state and next-state variables in asynchronous sequential circuits are customarily called
State variables and secondary variables
State variables
excitation variablesand secondary variables
secondary variables and excitation variables
The inputs in the PLD is given through
NAND gates
OR gates
NOR gates
AND gates
PLA refers to
Programmable Loaded Array
Programmable Logic Array
Programmable Array Logic
None of the above
PLAs, CPLDs, and FPGAs are all which type of device?
SLD
SRAM
PLD
EPROM
The difference between a PLA and a PAL is:
the PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a programmable AND plane
the PAL has a programmable OR plane and a programmable AND plane, while the PLA only has a programmable AND plane
the PAL has more possible product terms than the PLA
PALs and PLAs are the same.
The following map shown in Fig illustrates
Static-1-hazard
Static-0-hazard
Dynamic hazard
Essential hazard
How many different states does a 3-bit asynchronous counter have?
2
3
8
16
The difference between PLA and PROM
PLA is sequential PROM is combinational
PROM is sequential PLA is combinational
PLA economizes on the number of minterms to implement Boolean function
PLA has fixed AND
PROM has fixed OR
A=1 B=1 Q=0
A=0 B=1 Q=1
A=1 B=1 Q=1
A=0 B=0 Q=1
Write out the Boolean expression.
Q=NOT(A AND B)
AND C
Q=NOT(C AND B)
AND C
Q=OR(A)
AND C
Q=NOT(B)
OR Cd
Write out the boolean expression.
Q=(A AND B)
AND (C NOT D)
Q=(A OR B)
NOT (B OR D)
Q=(A NOT B) OR (C OR D)
Q=(A OR B)
AND (C OR D)
What does Boolean logic use?
(a)
1,1,1,0
0,0,01
1,0,0,1
1,1,1,1
With four signal inputs, how many possible outputs are there?
8
4
16
32
How do OR and XOR logic gates differ?
An OR gate always outputs 0 no matter what the inputs whereas an XOR outputs a 1 if one or more of the inputs is a 1
There is no difference
An OR gate outputs a 1 if one or more of the inputs is a 1 whilst an XOR outputs a 1 if only one (not both) of the inputs is a 1
Which of the following are logic gates?
OR, NOT, AND
OR, AND, XOR
OR, AND, XOR, NOT
free offer
free offer
The sequential circuits consists of
Combinational logic as well as memory elements
Combinational logic only
memory elements only
Logic Gates only
The example of sequential circuit is
Multiplexers
Decoders
7 Segment display
Counters
When the output of a sequential circuit depends on the present input as well as previous output states, then the circuit is called
Moore machine
Mealy Machine
Sequential circuit
Combinational circuit
A n bit shift register cannot be used as
Module n counter
Module 2n counter
Serial to parallel conversion
parallel to serial conversion
Generally shift register is constructed by using
T FF
SR FF
D FF
JK FF
The number of flip-flops are required for mod-5 counter
1
2
3
4
In design a counter circuit, the most commonly used flip-flop is
SR FF
D FF
JK FF
Latch
The minimum number of flip-flops required for a synchronous decade counter is
1
2
3
4
What is the modules of 5-bit ripple counter
16
32
64
128
A mod-2 counter, followed by a mod-5 counter is
mod-5 counter followed by a mod-2 counter
mod -9 counter
mod-11 counter
decade counter
A decade counter can be designed by
4 FF and by pass 6 states
10 FF and by pass 10 states
4 FF and by pass 5 states
4 FF and by pass 4 states
Three mod-5 counters are connected in cascaded. The overall modulus of circuit will be
Mod -10 counter
Mod -15 counter
Mod -125 counter
Mod -100 counter
A 4 bit counter requires
3 FF
4 FF
5 FF
6FF
The minimum propagation delay is possible in
Synchronous counter
Asynchronous counter
Shift register
None of these
The maximum number of states in 4 bit synchronous counters
4
8
10
16
