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Quiz-1

Total questions: 20

Worksheet time: 20mins

Name
Class
Date
1.

Minimum number of 2:1 multiplexers required to implement a 16:1 multiplexer

a)

8

b)

11

c)

15

d)

16

2.

Boolean expression for the output of following logic circuit is

a)

Y= A B' C+A B C

b)

Y= A B' C+A B C'

c)

Y= A B' C'+A' B C

d)

Y= A' B' C+A B C'

3.

Four books have cost of (1000)5, (1000)6, (1000)8 and (1000)16. What will be the cost of all four books in total?

a)

(4949)10

b)

(8049)10

c)

(4000)10

d)

(5049)10

4.

Decimal ranges of 1's and 2's compliment numbers which can be represented using 7 bits are

a)

0 to 127 and -64 to 63

b)

-63 to 63 and -64 to 63

c)

0 to 127 and -64 to 64

d)

-64 to 63 and -64 to 63

5.

Boolean function of following circuit is

a)

f(x,y,z)= {1, 2, 5, 6}

b)

f(x,y,z)= {0, 2, 5, 7}

c)

f(x,y,z)= {1, 2, 4, 6, 7}

d)

f(x,y,z)= {0,1, 2,3, 6}

6.

How many minimum number of  binary bits will be required to represent the smallest and biggest 4 digit decimal numbers respectively?

a)

10 and 15

b)

8 and 16

c)

10 and 14

d)

7 and 13

7.

Number of  AND gates to implement a 16 : 1 multiplexer and OR gates  to implement a Hexadecimal-to-binary encoder are respectively

a)

16, 8

b)

8, 16

c)

4, 16

d)

16, 4

8.

A common bus which shares the data from 8 registers, each of  width of 4-bit, can be implemented by using

a)

a decoder of size 3:8 and 12 tri-state buffers

b)

a encoder of size 8:3 and 32 tri-state buffers

c)

a encoder of size 8:3 and 8 tri-state buffers

d)

a decoder of size 3:8 and 32 tri-state buffers

9.

To realize an adder that can add two 16-bit numbers, how many full adders and half adders are required?

a)

10 half-adders and 17 full adders

b)

10 half-adders and 15 full adders

c)

15 half-adders and 1 full adders

d)

1 half-adders and 15 full adders

10.

How many AND, OR and XOR gates are required for the configuration of 32-bit ripple carry adder using full adder respectively?

a)

64, 64, 64

b)

64, 32, 64

c)

32, 32, 64

d)

64, 0, 64

11.

What must be the base to hold the equality of 4+2 =11

a)

4

b)

5

c)

6

d)

7

12.

A 16-bit half adder can be implemented by using

a)

32 Multiplexers each of size 2:1

b)

16 Multiplexers each of size 2:1

c)

32 Multiplexers each of size 4:1

d)

16 Multiplexers each of size 4:1

13.

Which one of the following is the 2's complement representation of decimal value 15?

a)

1111

b)

10111

c)

0001

d)

10001

14.

Number of  AND gates to implement a 16 : 1 multiplexer and OR gates  to implement a Hexadecimal-to-binary encoder are respectively

a)

16, 8

b)

8, 16

c)

4, 16

d)

16, 4

15.

Given that F=A'B' + C' +D' +E' , which of the following represent the correct expression for F' ?

a)

F' =A+B+C+D+E

b)

F' =(A+B)CDE

c)

F' =AB(C+D+E)

d)

F' =AB+C'+D'+E'

16.

What will be the effect on execution time, if both CPI and clock period of a computer system reduced to half?

a)

Reduces to one forth

b)

Reduces to one half

c)

Remains same

d)

Increases twice

17.

If a computer system consumes total power of 100 watt/h. How much you have to pay monthly @ Rs 5 if system is used 10 hours/day.

a)

500

b)

250

c)

100

d)

150

18.

Minimum number of bits required to represent one pixel of a grey and color image are respectively.

a)

8, 24

b)

8, 8

c)

16, 8

d)

24, 8

19.

If a processor uses clock rate of 4 GHz and CPI of 2.5. How many instructions can be executed by this system in MIPS?

a)

1000

b)

1200

c)

1600

d)

2000

20.

IEEE 754 single precision is given by 1 10000110 10100..00. Which one of the following represents the number in normalized unbiased binary format?

a)

- 1.101X27

b)

- 1.101X2-6

c)

- 1.0101X27

d)

- 1.110101X27