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WorksheetsFinal Fall 2022 (CEA201)
Total questions: 48
Worksheet time: 24mins
The _________ performs the computer's data processing functions.
system bus
Register
ALU
CPU interconnection
The method of calculating the EA is the same for both base-register addressing and indexing
True
False
The _______ holds the address of the next instruction to be fetched.
MBR
IR
PC
MAR
_______ are a set of storage locations.
Registers
Control units
PSWs
Processors
Interfaces between the computer and peripherals is an example of an organizational attribute
True
False
Which of the following memory types are nonvolatile ?
erasable ROM
programmable ROM
flash memory
all of the above
A _______ disk is permanently mounted in the disk drive, such as the hard disk in a personal computer.
removable
double sided
nonremovable
movable-head
A(n) ________ is generated by a failure such as power failure or memory parity error.
timer interrupt
hardware failure interrupt
I/O interrupt
program interrupt
The _______ determines the opcode and the operand specifiers.
decode instruction
fetch operands
calculate operands
execute instruction
I/O channels are commonly seen on microcomputers whereas I/O controllers are used on mainframes.
True
False
All DRAMS requires a refresh operation.
True
False
The performance of the cache memory is measured in terms of a quality called _________
Hit Ratio
Instruction Ratio
Miss Ratio
Initialization Ratio
Address Ratio
The ______ consists of the access time plus any additional time required before a second commence.
direct access
transfer rate
memory cycle time
latency
The data lines provide a path for moving data among system modules and are collectively called the _____
control bus
system bus
address bus
data bus
The basic functions of a computer is to execute programs.
True
False
An I/O device is referred to as a ________.
CPU
control device
register
peripheral
An I/O module must recognize one unique address for each peripheral it controls
True
False
Cycle stealing is/are used in which concept?
Programmed I/O
DMA
Interrupts
Memory mapped I/O
All of the above
With direct addressing, the length of the address field is usually less than the word length, thus limiting the address range.
True
False
What is stored in the Stack Pointer?
Address of the next instruction
Stack data values
Addressing method
Operations
Address of top item
The ______ interprets the instructions in memory and causes them to be executed.
I/O
control unit
main memory
arithmetic and logic unit
_______ is when the disk rotates more slowly for accesses near the outer edge than those near the center
Seek time
Magnetoresistive
Constant angular velocity (CAV)
Constant linear velocity (CLV)
The correspondence between the main memory blocks and those in the cache is specified by a _______
Segment function
Hit rate
Replacement algorithm
Mapping function
Miss penalty
The routine executed in response to an interrupt request is called _____ routine
Interrupt service
Interrupt acknowledge
Serial interrupt
Vectored interrupt
Sub-routine
The ______ controls the movement of data and instructions into and out of the processor.
control unit
ALU
shifter
branch
Counters can be designated as _______
asynchronous
neither asynchronous or synchronous
synchronous
both asynchronous and synchronous
The method of using the same lines for multiple purposes is known as time multiplexing
True
False
________ registers may be used only to hold data and cannot be employed in the calculation of address
General purpose
Condition code
Data
Address
The ______ defines the system call interface to the operating system and the hardware resources and services available in a system through the user instruction set architecture.
API
ISA
ABI
HLL
The predict-never-taken approach is the most popular of all the branch prediction methods.
True
False
Both batch multiprogramming and time sharing use multiprogramming
True
False
The instruction location immediately following the delayed branch is referred to as the ________
delay load
delay file
delay register
delay slot
Architectural attributes include ______
memory technology used
interfaces
control signals
I/O mechanisms
Second generations computer used ________
integrated circuits
large-scale integration
transistors
vacuum tubes
A common of system interconnection is by means of a _______
data transport
control device
register
system bus
A bus that connects major computer components (processor, memory, I/O) is called a _______
control bus
system bus
data bus
address bus
The register files employs much shorter addresses than addresses for cache and memory
True
False
Because data are striped in very small strips, RAID 3 cannot achieve very high data transfer rates
True
False
______ is a principle by which two variables are independent of each other
Autoindexing
Opcode
Completeness
Orthogonality
With a batch operating system the user does not have direct access to the processor
True
False
When using graph coloring, nodes that share the same color cannot be assigned to the same register.
True
False
The most important system program is the OS.
True
False
Three of the most common uses of stack addressing are relative addressing, base-register addressing, and indexing.
True
False
The unary operation ______ inverts the value of its operand.
XOR
NAND
NOT
OR
Consider a magnetic disk drive with 4 surfaces, 512 tracks per surface, and 32 sectors per track, a sector is 512 byte. What is the disk capacity ?
32 MB
512 KB
64 KB
16 GB
64 MB
The cache is capable of handling global as well as local variables.
True
False
A number of chips can be grouped together to form a memory bank.
True
False
The ABI is the boundary between hardware and software.
True
False
