Font size
WorksheetsPost-Test CPE15 - HDL
Total questions: 65
Worksheet time: 3hrs 1mins
It is a set of notations, similar to software programming languages, used for modeling the logical function of digital circuits and systems.
PL
HPL
HDL
MS
The full form of HDL is _________________
Higher Descriptive Language
Higher Definition Language
Hardware Description Language
High Descriptive Language
The Verilog HDL code starts with the keyword_________
always
module
endmodule
items
The Verilog HDL code ends with the keyword_________
always
module
keys
endmodule
Different types of modelling in Verilog HDL are _____
Gate level, Data flow and Behavioral
data, case and type
Gate, Logic and gates
None
The symbol used for Logical AND operation is ______
and
or
&&
None
A simulator interprets the HDL description and produces a readable output, such as a timing diagram, that predicts how the hardware will behave before its is actually fabricated.
HDL
Verilog
VHDL
Logic Synthesis tool
What are the building blocks of any digital system?
Logic Gates
Resistors
Integrated Circuits
Transistors
Which one of the following is a VHDL logical (Boolean) operator?
Equality
Inequality
Less than
Not
Which one of the following is a VHDL shift operator?
SLA
Not equal
Equal
None of the above
The simple index: integer: =0 is an example declaration of _______________ data type provided within VHDL?
Integer
Real
Boolean
Character
Which one of the following is a type of scalar literal?
Character
String
Bit_vector
Both b and c
In which one of the following, the user defined data types are allowed?
VHDL
Verilog
Both a and b
None of the above
In which one of the following, the modulo operator is present?
VHDL
Verilog
Both a and b
None of the above
Which one of the following, one manages the large design?
VHDL
Verilog
Both a and b
None of the above
Which one of the following modelling statements consists of sequential program statement?
Behavioural
Dataflow
Both a and b
None of the above
The variable Val: real: =1.0 is an example declaration of ______ data type provided within VHDL?
Integer
Real
Boolean
Character
Which one of the following VHDL design unit used to define external view of a model?
Entity
Architecture
Configuration
None of the above
Which one of the following modelling statements consists of concurrent statements?
Structural
Dataflow
Both a and b
None of the above
Which one of the calls are used in the Verilog program?
Procedure calls
Task calls
Both a and b
None of the above
Which one of the calls are used in the VHDL program?
Procedure calls
Task calls
Both a and b
None of the above
Which of the following codes are simplified by using procedures?
VHDL
Verilog
Both a and b
None of the above
Which one of the following object types require less memory?
Signals
Variables
Both a and b
None of the above
Which one of the following VHDL design unit is used to define the function of the model?
Entity
Architecture
Configuration
None of the above
The variable term: character: ='@' is a _____?
Integer
Real
Boolean
Character
Which one of the following VHDL design unit used to associate an architecture with an entity?
Entity
Architecture
Configuration
None of the above
The figure shown below is a block diagram of ____________________?
Verilog
VHDL
HDL
None of the above
The Verilog is modelled for the ________ devices.
condution
electrical
electronics
All of the above
_________ hardware description language is more flexible.
C
Java
Verilog
VHDL
The Verilog can provide transistor-level descriptions but the VHDL cannot provide this description.
Yes
No
May be
Can't say
________ is used to introduce delays in a circuit.
Flip-flops
EXOR gate
Inverter
Buffer
The possible values of the == operator are __________.
0
1
x
All of the above
Which mistakes are contained in the following code?
out is missing from port declaration (it should be an input port)
clk should be in the port list
reg in should be reg [3:0] in
4) endmodule is missing
This design needs a reset
What can be the various uses of VHDL?
What are HDL simulators?
Verilog
VHDL
SystemVerilog
All of the above
What do you understand by $monitor, $display, and $strobe? (Select three (3) answers that may apply)
The $monitor, $display, and $strobe are not a commands with similar syntax and show text on the screen while running a simulation
The $monitor command is used to display each time you change one of the parameters
The $display command displays the parameters when you execute it
The $strobe command is used to display the parameters after the current simulation time unit
In what aspect, HDLs differ from other computer programming languages?
No aspect; both are same
HDLs describe hardware rather than executing a program on a computer
HDLs describe software and not hardware
Other computer programming languages have more complexity
Which of the following HDLs are IEEE standards?
VHDL and Verilog
C and C++
Altera and Xilinx
Quartus II and MaxPlus II
Why we needed HDLs while having many traditional Programming languages?
Traditional programming languages are complex
HDLs are complementary to traditional programming languages to complete the design process
Some characteristics of digital hardware couldn’t be captured by traditional languages
HDLs offer more complexity than traditional programming languages.
An HDL can’t describe Hardware at Gate level as well as switch level?
True
False
Maybe
Can't say
Why do we need concurrent processing for describing digital systems in HDLs?
Faster processing than conventional programming languages
Concurrent processing is easier than sequential processing
It allows taking timing constraints into consideration
Complexity of digital systems needs concurrent processing
What is the advantage of using VHDL instead of any other HDL?
Week typing
Based on ADA
Portability
Easy to code
Which of the following is a characteristic of VHDL?
Case sensitive
Use of simple data types
Based on C programming language
Strongly typed language
Which of the following is a characteristic of Verilog HDL?
Strongly typed language
Case sensitive
Better library
Not portable
A package in VHDL consists of _________
Commonly used architectures
Commonly used tools
Commonly used data types and subroutines
Commonly used syntax and variables
Which of the following describes the structure of VHDL code correctly?
Library Declaration; Entity Declaration; Architecture Declaration; Configurations
Entity Declaration; Configuration; Library Declaration; Architecture Declaration
Configuration; Library Declaration; Entity Declaration; Architecture Declaration
Library Declaration; Configuration; Entity Declaration; Architecture Declaration
Which of the following statement is true?
Package is a collection of Libraries
Library is a collection of Packages
Entity is a collection of Packages
Architecture is a collection of Entities
Which of the following is correctly declared library for VHDL code?
LIBRARY library_name; USE package_name.parts;
LIBRARY package_name.parts; LIBRARY library_name;
USE library_name; LIBRARY library_name.package_name.parts
LIBRARY library_name; USE library_name.package_name.parts
Which of the following is correct syntax for entity declaration?
Refer to the VHDL code given below, how many input-output pins are there in MUX entity?
5
4
3
2
Which of the following is the correct syntax for architecture declaration and definition?
The statements in between the keyword BEGIN and END are called _______
Concurrent statements
Netlist
Declaration statement
Entity function
Which of the following is the correct architecture for a simple Nand gate?
What does an arrow indicate in the schematic format of process statement given below?
Variable declaration
Process body
Process label
Sensitivity list
The ability of HDL to describe the performance specification of a circuit is regarded as ____
Test case
System case
Mark bench
Test bench
In the following code, which of the lines corresponds to the function call and function definition?
L3, L5
L5, L3
L3, L7
L5, L9
The structural code for 4-bit adder is given below
output
component
input
n
How many types of output are returned by the given
0
1
2
3
What will be the value of the statements given?
red
blue
yellow
black
What is the type of modeling used in the code given below?
Behavioral
Dataflow
Structural
Combinational
The architecture describes _______ gate implemented by _________ modeling.
Or, behavioral
Not, Dataflow
Nor, behavioral
Nor, Dataflow
Which of the following line contain error?
L2
L3
L4
No error
What is the function of this code
To perform binary multiplication of two data inputs
To count the number of ones in the given data
To count the number of zeroes in the given data
To reverse the order of the given data
In ______ counter universal clock is not used
decade counter
ring counter
synchronous counter
asynchronous counter
Which of the following can't be implemented with concurrent statements only?
Counter
Decoder
Adder
Multiplexer
