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WorksheetsHùng đẹp trai
Total questions: 56
Worksheet time: 19mins
Name
Class
Date
1.
Câu 1. What is NOT the correct statement about ROM and RAM?
a)
a.The information can only be read from ROM while the information can be read from and write to RAM.
b)
b.ROM is read only memory and RAM is random access memory.
c)
b.ROM is read only memory and RAM is random access memory.
d)
d.ROM is only used to store instructions while RAM is only used to store instructions and data.
e)
Pluto
2.
Câu 2. What is the correct name of AGP bus?
a)
a.Advanced Graph Port
b)
b.Accelerated Graphics Port
c)
b.Accelerated Graphics Port
d)
d.Advanced Graphics Port
3.
Câu 3. What is the correct name of NAS storage system?
a)
a.Network Attacked Storage
b)
b.Net Attached Storage
c)
b.Net Attached Storage
d)
d.Network Attached Storage
4.
Câu 4. What are the characteristics of the cache set associative mapping technique?
a)
a.Simple, fast and fixed mapping
b)
b.Complicated, fast and flexible mapping
c)
b.Complicated, fast and flexible mapping
d)
d.Simple, slow and flexible mapping
5.
Câu 5. Which is the increment order of memory components in accessing speed?
a)
a.RAM, Cache, Registers, HDD, SSD
b)
b.HDD, SSD, RAM, Cache, Registers
c)
b.HDD, SSD, RAM, Cache, Registers
d)
d.HDD, SSD, RAM, Registers, Cache
6.
Câu 6. In CPU pipeline, the delayed branching technique is suitable for...
a)
a.very long pipelines.
b)
b.medium pipelines.
c)
b.medium pipelines.
d)
d. long pipelines.
7.
Câu 7. What is the technique used in RAID 0?
a)
a.Disk striping
b)
b.Disk striping and disk mirroring
c)
b.Disk striping and disk mirroring
d)
d.Disk striping or disk mirroring
8.
Câu 8. Why can multi-level cache give better performance than one level cache?
a)
a.Because it can make the speed of main memory faster.
b)
b.Because it can balance the speed of CPU and RAM memory better.
c)
b.Because it can balance the speed of CPU and RAM memory better.
d)
d.Because it can balance the volume of CPU and main memory better
9.
Câu 9. What are two basic techniques used in RAID storage system?
a)
a.Disk straping, Disk mirroring
b)
b.Disk striping, Disk rotating
c)
b.Disk striping, Disk rotating
d)
d.Disk striping, Disk mirroring
10.
Câu 10. What are the functions of computer keyboards?
a)
a.Input data and Storage
b)
b.Input data and Control
c)
b.Input data and Control
d)
d.Import data and Storage
11.
Câu 11. Why is cache is considered a smart memory?
a)
a.Because cache is a very fast memory.
b)
b.Because cache can load enough instruction and data for CPU.
c)
b.Because cache can load enough instruction and data for CPU.
d)
d.Because cache can reduce the memory access time.
12.
Câu 12. The Control Unit (CU) decodes the instruction and generates ... for other units, such as ALU to execute the instruction.
a)
a.execution signal
b)
b.pulse
c)
b.pulse
d)
d.request
13.
Nonee
a)
1
b)
1
14.
None
a)
1
b)
1
15.
Câu 14. CPU instruction is a ... which implements a single pre-defined operation of a processor.
a)
a.binary code
b)
b.machine code
c)
b.machine code
d)
d.hexa word
16.
Câu 15. In look aside architecture, cache and memory are connected to ... and they "see" the CPU bus cycle...
a)
b.system bus / at the same time.
b)
c.internal bus / at the same time.
c)
c.internal bus / at the same time.
17.
Câu 16. Storage Area Network (SAN) is ... which is dedicated for storage services.
a)
a.a group of servers
b)
b.a number of servers
c)
b.a number of servers
d)
d.a number of machines
18.
Câu 17. What are data transfer speeds of v1.x, v2.0, v3.0 PCIe 16 lanes?
a)
a.4GB/s, 8GB/s, 12GB/s
b)
b.4GB/s, 8GB/s, 16GB/s
c)
b.4GB/s, 8GB/s, 16GB/s
d)
d.8GB/s, 12GB/s, 16GB/s
19.
Câu 18. PCI bus uses parallel communication type. What is the communication type of PCIe bus?
a)
b.Parallel
b)
c.Point to multi-point
c)
c.Point to multi-point
20.
Câu 19. What are the characteristics of magnetic disks?
a)
a.volatile, hard storage, based on magnetic principles
b)
b.Non-volatile, mass storage, based on magnetic principles
c)
b.Non-volatile, mass storage, based on magnetic principles
d)
d.Non-volatile, mass storage, based on ferromagnetic principles
21.
Câu 20. What is the number of addresses of operands of the instruction "ADD R1, A", where R1 is a CPU register and A is a memory location?
a)
b.1
b)
c.2.5
c)
c.2.5
22.
Câu 21. System Design which includes all of the other hardware components within a computing system, such as…
a)
a.System connects and CPU off-load mechanisms.
b)
b.System connects and CPU on-load mechanisms.
c)
b.System connects and CPU on-load mechanisms.
d)
d.System interconnects and CPU off-load mechanisms.
23.
Câu 22. SP or Stack Pointer is the register that always points to ... of the stack.
a)
a.next frame
b)
b.the middle
c)
b.the middle
d)
d.the top
24.
Câu 23. What are the capacity of standard CD-ROM and DVD-ROM?
a)
a.650MB and 4.5GB
b)
b.720MB and 4.8GB
c)
b.720MB and 4.8GB
d)
d.750MB and 4.2GB
25.
Câu 24. What are components participated in reading information from CD-ROMs?
a)
a.Laser diode, beam split, laser source, mirror rotation
b)
b.Laser diot, beam split, laser source, rotation mirror
c)
b.Laser diot, beam split, laser source, rotation mirror
d)
d.Laser diode, beam splitter, laser sensor, rotation mirror
26.
Câu 25. The number of addresses of operands of instructions may be 3,…
a)
a.2, 1, 1.5 and 0.
b)
b.2, 1, 0.5 and 0.
c)
b.2, 1, 0.5 and 0.
d)
d.2.5, 2, 1 and 0.
27.
Câu 26. What is the addressing mode of the instruction "LOAD Ri, X(PC)", where Ri is a CPU register?
a)
a.Relative
b)
b.Indirect
c)
b.Indirect
d)
d.Direct
28.
Câu 27. The computer input and output devices are also called ... devices.
a)
a. peripheral
b)
b. internal
c)
b. internal
d)
d. periphered
29.
Câu 28. What is the addressing mode of the instruction "LOAD R1, 1000", where R1 is a CPU register?
a)
a. Indirect
b)
b. Relative
c)
b. Relative
d)
d. Immediate
30.
Câu 29. CRT monitor uses the ... emitted from its cathode to ... layers to create pictures.
a)
a. electronic beam / phosphor
b)
b. electron beam / phophor
c)
b. electron beam / phophor
d)
d. electric beam / phosphor
31.
Câu 30.What is an input peripheral device for computers?
a)
a. CD-RW drive
b)
b. Monitor
c)
b. Monitor
d)
d. Printer
32.
Câu 31. What is an output peripheral device for computers?
a)
a. CD-R drive
b)
b. Mouse
c)
b. Mouse
d)
d. Scanner
33.
Câu 32.Which is a true statement about the performance role of cache memory?
a)
a. Cache increases the speed of main memory to meet the CPU speed.
b)
b. Cache reduces the fast speed of CPU to meet the slow speed of main memory.
c)
b. Cache reduces the fast speed of CPU to meet the slow speed of main memory.
d)
d. Cache balances the fast speed of CPU and the slow speed of main memory.
34.
Câu 33.Cache exchanges ... with CPU while it exchanges ... with main memory.
a)
a. individual data / blocked data
b)
b. individual data items / data blocks
c)
b. individual data items / data blocks
d)
d. instruction items/instruction blocks
35.
Câu 34.Common groups of CPU intructions include...
a)
a. data movement group, arithmetic group, conditional and branching group.
b)
b. data movement group, computational group, conditional and looping group.
c)
b. data movement group, computational group, conditional and looping group.
d)
d. data movement group, computational group, conditional and branching group.
36.
Câu 35.What are advantages of SSDs over HDDs in computers?
a)
a. Higher accessing, Less expensive, More compact in size
b)
b. Higher accessing speed, Less power consumption, Less compact in size
c)
b. Higher accessing speed, Less power consumption, Less compact in size
d)
d. Higher accessing speed, Less power consumption, More compact in size
37.
Câu 36.What are the characteristics of RAM memory?
a)
a. Volatile memory, semiconductor memory, random access memory
b)
b. Non-volatile memory, semiconductor memory, random access memory
c)
b. Non-volatile memory, semiconductor memory, random access memory
d)
d. Non-volatile memory, semiconductor memory, random access memory
38.
Câu 37.SRAM is faster than DRAM because its bits have the ... and SRAM chips accept all address bits at a time.
a)
a. symmetric architecture
b)
b. symmetric structure
c)
b. symmetric structure
d)
d. complex architecture
39.
Câu 38.In CPU pipeline, the instruction execution is divided into stages and.... is executed by...
a)
a. each stage / a CPU component.
b)
b. CPU components / stages.
c)
b. CPU components / stages.
d)
d. stages/CPU components.
40.
Câu 39.In cache temporal locality, if a memory location is accessed, the probability that it is... is high.
a)
a. not accessed in near future
b)
b. not accessed again in near future
c)
b. not accessed again in near future
d)
d. accessed in near future
41.
Câu 40.Cache works based on 2 basic principles, including...
a)
a. spatial locality and time locality.
b)
b. space locality and time locality.
c)
b. space locality and time locality.
d)
d. space locality and temporal locality.
42.
Câu 41.Which is NOT a correct statement about CPU instructions?
a)
a. Instructions are saved from CPU to memory after execution.
b)
b. Instructions are fetched from memory to CPU for execution.
c)
b. Instructions are fetched from memory to CPU for execution.
d)
d. One instruction has it own function.
43.
Câu 42.Internal Bus is the communication channel of all CPU components. It supports ... ways of communication.
a)
a. three
b)
b. two
c)
b. two
d)
d. one
44.
Câu 43.What is the communication speed of USB 3.0 ports?
a)
a. 2.0Gb/s
b)
b. 1.5Gb/s
c)
b. 1.5Gb/s
d)
d.1Gb/s
45.
Câu 44.What type of pipeline conflicts is it, in which a program have instructions, such as JUMP, CALL and RETURN?
a)
a. Data conflict
b)
b. No conflict
c)
b. No conflict
d)
d. Branching conflict
46.
Câu 45. What is NOT a component of the instruction set architecture?
a)
a. Memory addressing modes
b)
b. Address format
c)
b. Address format
d)
d. The instruction set
47.
Câu 46.Cache is a memory element in the computer memory hierarchy and it acts as the ... between CPU and the main memory.
a)
a. intermediary
b)
b. storage
c)
b. storage
d)
d. memory
48.
Câu 47.What is the meaning of the instruction "ADD A, B, C", where A, B, C are memory locations?
a)
1
b)
1
49.
Câu 48.What is the data transfer speed of the third SATA interface generation?
a)
a. 6 Gb/s
b)
b. 8 Gb/s
c)
b. 8 Gb/s
d)
d. 4 Gb/s
50.
Câu 49.Two major types of RAM memories are...
a)
a. RAM, DDR RAM.
b)
b. SAM, DRAM.
c)
b. SAM, DRAM.
d)
d. SRAM, DRAM.
51.
Câu 50.What is the correct name of PCI bus?
a)
a. Peripher Component Interface
b)
b. Peripher Component Interconnect
c)
b. Peripher Component Interconnect
d)
d. Peripheral Component Interface
52.
Câu 51.Why does DRAM memory need periodic refresh?
a)
a. Because electric charge in the capacitor of DRAM bits is leaking by nature.
b)
b. Because information stored in DRAM is removed automatically.
c)
b. Because information stored in DRAM is removed automatically.
d)
d. Because electric charge stored in DRAM is removed automatically.
53.
Câu 52.Each bit of FR register stores the ... of the operation executed by ALU.
a)
a. result
b)
b. status of the result
c)
b. status of the result
d)
d. state of the result
54.
Câu 53. Which is NOT a true memory type based on access types?
a)
a. Read Only Memory
b)
b. Magnetic memory
c)
b. Magnetic memory
d)
d. Random Access Memory
55.
Câu 54.What are clock speeds of ISA buses?
a)
a. 4MHz, 6MHz, 8MHz
b)
b. 6MHz, 8MHz, 10MHz
c)
b. 6MHz, 8MHz, 10MHz
d)
d. 8MHz, 10MHz, 12MHz, 14MHz
56.
Câu 55. What are characteristics of cache memory?
a)
a. fast, small in size, low cost per bit
b)
b. very fast, small in size, very high cost per bit
c)
b. very fast, small in size, very high cost per bit
d)
d. very fast, small in size, high cost per bit
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