WorksheetsCEA201 (1)
Total questions: 52
Worksheet time: 26mins
Within the processor there is a set of registers that function as a level of memory above main memory and ache in the hierarchy
False
True
With the IAS computer, what is the main function of ALU (Arithmetic and Logic Unit)?
a.Compute the operations of a program
b.Store both data and instruction
c.None of them
d.Operating on binary data by an instruction
With the fully associative mapping method, assume that the computer system has 2GB of main memory size, 128KB of cache size, and 16 bytes of cache lines. Calculate the number of bits for Tag, and Word Fields
Tag: 31 bits; Word: 4 bits
Tag: 28 bits; Word: 5 bits
Tag: 27 bits; Word: 4 bits
None of them
With the direct mapping method, assume that the computer system has 2GB of main memory size, 128KB of cache size, and 16 bytes of cache lines. Calculate the number of bits for Tag, Line, and Word Fields
Tag: 12 bits; Line: 13 bits; Word: 5 bits
Tag: 14 bits; Line: 13 bits; Word: 5 bits
Tag: 13 bits; Line: 13 bits; Word: 5 bits
None of them
With parallelizing computation, how many general approaches are there?
None of them
4
5
3
With direct addressing, the length of the address field is usually less than the word length, address range.
True
False
With direct addressing, the length of the address field is usually less than the word length, thus limiting the address range.
True
False
With demand paging it is necessary to load an entire process into main memory.
True
False
With a batch operating system the user does not have direct access to the processor.
True
False
With a batch operating system the user does not have direct access to the processor
True
False
Why is SRAM used for cache memory, not DRAM?
Because of its design with many memory cells
Because of its power consumption is smaller than DRAM
Because of its speed faster than DRAM by using only transistor in design
Which properties do all semiconductor memory cells share?
they are capable of being read to sense the state
all of the above
they exhibit two stable states which can be used to represent binary 1 and 0
they are capable of being written into to set the state
Which of the following memory types are nonvolatile?
all of the above
programmable ROM
erasable PROM
flash memory
When using technique, all write operations are made to main memory as well as to the cache, ensuring that main memory is always valid
LRU
write through
unified cache
write back
When using graph coloring, nodes that share the same color cannot be assigned the same.
T
F
When the magnetizable coating is applied to both sides of the platter the disk is then referred to as …
double sided
all of the above
substrate
multiple sided
When large volumes of data are to be moved, a more efficient technique is direct memory access (DMA).
T
F
When data is moved over longer distances, to or from a remote device, the process is known as____________.
registering
structuring
data communications
data transport
What is user-visible register?
None of them
Enable the machine-or assembly language programmer to minimize main memory
To assign a variety of functions by the programmer
To control the operation of the processor an by privileged
What is the purpose of tags in mapping method?
Identify which subset of the blocks of memory to reside in lines of cache
Identify which particular block is currently being stored in each line of cache
Identify which the block of memory is read and transferred to one of the lines of the cache
What is the maximum number of one-operand instructions that can be supported?
256
128
32
512
What is the machine cycle?
None of them
To be the time it takes to fetch two operations from registers, perform an ALU operation, and store the result in a register
To speed up in the execution of complex functions
Provide such instructions but also include memory-to-memory and mixed register/memory operations
What is the advantage of the DMA method?
None of them
Extent a t the expense of the I/O transfer rate
Tie up in managing an I/O transfer and number of instructions
Increase the I/O transfer rate for large volumes of data to be moved
What is the advantage of DMA method?
When extracting data from main memory and storing data in main memory for input
To reduce the wait time of processor for the I/O module of concern to be ready for either reception or transmission of data
When large volumes of data are to be moved
None of them
What is stored in the Stack Pointer?
Address of next instruction
Stack data values
Addressing method
Operations
Address of top item
What does the Programmable ROM (PROM) belong to the semiconductor memory types?
Read-only memory, possible erasure by electrical signal, write data by electrical signal, and volatile
Read-mostly memory, possible erasure by UV light, write data by electrical signal, and nonvolatile
Read-only memory, not possible erasure, write data by electrical signal, and nonvolatile
What does syndrome mean in Hamming code method?
The total of parity bit is done by two inputs
The checksum bit is generated by XOR operation in a comparison of two inputs
The result of a bit-by-bit comparison is done by taking the XOR of two inputs
The result of a XOR operation is done by two inputs
What are the internal structure of a computer?
Processor, Main memory, I/O device, and Bus
CPU, Main memory, I/O, and System interconnection
CPU, Register, I/O, and System Bus
What are NOT the services that OS typically provides?
Program execution
Accounting
Program creation
Controlled access to files
Compile program
Using Karnaugh map to simplify the Boolean Function below:F(A,B,C) = Sigma(3,4,5,6,7)Note A = MSB and at the 7th position in decimal, it gets a "d" value (do not care condition)
F(A,B,C) = A' + BC'
F(A,B,C) = A + B'C
F(A,B,C) = A + BC
None of them
Using algebraic simplification method and equality to simplify the Boolean function below:F(A,B,C) = ABC + ABC' + AB'C
None of them
F(A,B,C) = A + BC
F(A,B,C) = AB + C
F(A,B,C) = A(B+C)
Timing refers to the way in which events are coordinated on the bus.
T
F
Three of the most common uses of stack addressing are relative addressing, base-register indexing.
T
F
The… cycle occurs at the beginning of each instruction cycle and causes an instruction to be fetched from memory.
indirect
fetch
interrupt
execute
The… contains the 8-bit opcode instruction being executed.
instruction register
instruction buffer register
memory buffer register
memory address register
The von Neumann architecture is based on which concept?
all of the above
data and instructions are stored in a single read-write memory
the contents of this memory are addressable by location
execution occurs in a sequential fashion
The value of the mode field determines which addressing mode is to be used.
T
F
The unary operation inverts the value of its operand.
XOR
NAND
NOT
OR
The System bus is made up of A Control bus
Address bus
Both Control bus and Address bus
Control bus, Data bus and Address bus
Data bus
The System bus is made up of.....
Control bus, Data bus and Address bus
Address bus
Control bus
Both Control bus and Address bus
Data bus
The sum of the seek time and the rotational delay equals the … which is the time it takes to get into position to read or write.
access time
gap time
constant angular velocity
transfer time
The set of all the tracks in the same relative position on the platter is called _______
Intertrack
Sectors
Cylinder
Multiple platter
The routine executed in response to an interrupt request is called … routine.
Interrupt Service
Vectored interrupt
Sub-routine
Serial interrupt
Interrupt acknowledge
The register file employs much shorter addresses than addresses for cache and memory.
T
F
The processor interprets the instruction and performs the required action into four categories_________
None of them
Processor-I/O, data processing, control
Processor-memory, processor-I/O, data processing, control
Data storage, data processing, data movements, and control
The principal advantage of_______ addressing is that it is a very simple form of addressing.
stack
register
direct
Displacement
The predict-never-taken approach is the most popular of all the branch prediction methods.
T
F
The performs the computer's data processing functions.
ALU
CPU interconnection
Register
System bus
The performance of the cache memory is measured in terms of a quantity called
Hit Ratio
Initialization Ratio
Instruction Ratio
Miss Ratio
Address Ratio
The operation …yields true if either or both of its operands are true.
NOT
AND
OR
NAND
The operand _________ yields true if and only if both of its operands are true.
XOR
OR
NOT
AND
The only form of addressing for branch instructions is … addressing.
base
relative
register
immediate
