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WorksheetsEC Internship Quiz
Total questions: 75
Worksheet time: 38mins
Which one is active low pin
PGM
I2C
MCLR
VSS
Name the type of architecture followed in PIC16F877A
Autonomous Architecture
Von Neumann
Harvard
None of the above
How many interrupt dose PIC have
3
6
14
8
BOR Stands for
Black out reset
Brown out reset
Black over reset
Brown over reset
What is P in PIC indicating
Programmable
Programmer
Peripheral
None
PC in PIC 16F877A is
Program Controller
13 bit
Peripheral
None
TRISE register are
Not the part of PIC microcontroller
Used to display the output
Available in Bank 1
Not aware of the register
CCP Modules are
One in numbers
Three in numbers
capable of producing PWM output.
None of the above.
Reset activates when
0 volts are received at MCLR
5 volts are received at MCLR
When voltage drops below 5 volts
All the above
PIC works when
It receives 0 volt at MCLR
It receives 5 volt at MCLR
MCLR is only for resetting, it doesn't control the working of PIC
All of the above
Which of the following is the fastest, smallest, and cheapest per unit to implement a given complex circuit in large volume?
FPGA
ASIC
PLA
CPLD
How many bits are in a single Binary Coded Decimal digit?
10 bits
2 bits
4 bits
8 bits
What is the basic unit of storage in a digital circuit?
Ouroborous NOT storage unit
Flip Flop
Transistor-capactior storage unit
Magnetic storage
Combinational logic is implemented on FPGAs using __.
Robotic Arm
Look Up Tables (LUTs)
Microcontrollers (uCs)
Multiplexers (MUXs)
The variant of 7 segment display used in the session ____.
Red
Green
Common anode
Common cathode
The EDA software used in this session ___.
Xilinx ISE
Altera Quartus
Xilinx Vitis Suite
Xilinx Vivado suite
Circuits which depend on both current inputs and previous inputs/state to determine the output are called ____
Combinational circuits
Impulse invariant circuits
Sequential circuits
Relay circuits
Clock signals are mandatory in ____
Asynchronous circuits
Synchronous circuits
Coherent circuits
Quadrature circuits
The clock edge used to shift the serial input bits into the register ____.
Falling(Negative) Edge
Rising(Positive) Edge
High State
Low State
Verilog is a ____
Software Description Language
Hardware Description Language
Transaction Level Langauge
Assembly Language
What is an Instruction Set Architecture?
Set of instructions executable by a CPU following it
Set of rules for the chipset to interface with the CPU
Specifications for the instruction memory architecture
Instructions for building a PC
Does Verilog run on the integrated circuit designed?
Yes, it runs on a boot loader chip
Yes, it runs on the IC designed
No, it is a framework for writing C++ code to make a processor on an FPGA
No, it is a set of instructions for a fab process or for an FPGA
A simple Arithmetic and Logic Units are an example of a/an ____
Combinational Digital circuit
Sequential Digital circuit
Analog circuit
Mixed signal circuit
The code written in a Verilog test bench is ___
Synthesizable
Non-synthesizable
Implementable
None of the above
What is RTL Design?
Resistor Transistor Logic design
Real-Time Logic design
Reduced Transistor Latency design
Register Transfer Level design
When NMOS gate is connected to +ve
channel will be formed
starts to conduct
starts to burn
none of the above
Choose the semi custom ASIC
channeled gate arry
FPGA
PLD
all the above
The VLSI design flow starts with:
RTL synthesis
Product specifications
Library mapping
What is the criterion of full custom design?
programmed by user
not required mask design
all mask design is new without use library
MOS transistor structure is ____________
a) symmetrical
b) non symmetrical
c) semi symmetrical
d) pseudo symmetrical
Which is used for the interconnection from source and drain in nMOS or pMOS ?
a) boron
b) oxygen
c) aluminium
d) silicon
In a CARRY LOOK AHAEAD ADDER, carry generate (G)and carry propagate functions (P) can be realized by using
OR and AND gates respectively
AND and XOR gates respectively
NAND and NOR gates respectively
XOR and XNOR gates respectively
The IC package pins can be directly soldered on the PCB; this method is called
surface-mounted technology
surface-mounted technique
surface-module technology
surface-mounted technique
The capacitances in MOSFET occurs due to:
Interconnects
Difference in Doping concentration
Difference in dopant materials
All of the mentioned
Intel currently has a CMOS technology process in which λ = 11 nm. What is the minimum size of the transistor?
11 nm
22 nm
33 nm
44 nm
Which design contains only the interconnections designed?
full custom design
semi-custom design
gate array design
transistor design
Xilinx based FPGA device are
RAM based
Non-Volatile EPROM based
Fuse- based
Array based
Xilinx XC3000 CLB includes
16 bit look up table
32 bit look up table
6 inputs to CLB
Propagation delay is variable
Density of FPGA includes
Upto 10 million gates
Upto 1 million gates
Upto 10000 gates
Upto 1 lakh gates
Which company fabricated the first IC?
Intel
Fairchild
Microsoft
……………. cannot be fabricated on an IC
Resistors
Diodes
Transistors
Inductors and Capacitors
The main differences between FPGA and ASIC is/are
The interconnects in FPGA are reconfigurable
Area, speed and power of ASIC are optimized.
For the similar digital designs, the speed and power consumption in ASIC are usually less.
FPGA Based design occupies more area than ASIC-Based design
SRAM -based devices are better than Antifuse -Based devices for military and aerospace applications
True
False
The difference between FPGA and PLD is that __________
FPGA is slower than PLD
FPGA has high power dissipation
FPGA incorporates logic blocks
All of the Mentioned
The inputs in the PLD is given through ____________
NAND gates
OR gates
NOR gates
AND gates
Size of the die is determined using
transistor size
inverter size
area of the circuitry
length of the circuitry
Hold time is defined as the time required for the data to ________ after the triggering edge of clock
Increase
Decrease
Remain stable
All of the above
An Antifuse programming technology is predominantly associated with _____.
PLDs
FPGAs
CPLDs
All of the above
If the level of fan-out is beyond a limit in synthesis, it results in an insertion of buffer by ultimate effect of _____ the speed.
Enhancing
Reducing
Stabilizing
None of the above
The devices which are based on fusible link or antifuse are _________time/s programmable.
One
Two
Four
Infinite
In floorplanning, which phase/s play/s a crucial role in minimizing the ASIC area and the interconnection density?
Placement
Global routing
Detailed routing
All of the above
An antifuse element initial provides ______ between two conductors in absence of the application of sufficient programming voltage.
Conduction
Insulation
Both A and B
None of the above
In a chip, which type/s of pad design/s is/are adopted to solve the problem of pin count?
Input pad design
Output pad design
Three state pad design
All of the above
In CMOS circuits, which type of power dissipation occurs due to switching of transient current and charging & discharging of load capacitance?
Static dissipation
Dynamic dissipation
Both a and b
None of the above
Which factor/s play/s a crucial role in determining the speed of CMOS logic gate?
Gain factor of MOS
Load capacitance
Power supply
All of the above
The ratio of PMOS and NOS transistor size of an inverter is___
1/1
2/1
4/1
1/2
Altera FPGAs use ____ programming technology.
EPROM
Anti-fuse
SRAM
DRAM
Actel FPGA uses _______ for programming.
Fuses
Anti-fuses
EPROM
SRAM
Compared to FPGA, ASIC consumes______power and _____.
low,faster
high,faster
high,slower
low,slow
In floorplanning, placement and routing are __________ tools.
Front end
Back end
Both a and b
None
Which among the following is/are not suitable for in-system programming?
EPROM
EEPROM
Flash
All of the above
In enhancement MOSFET, the magnitude of output current __________ due to an increase in the magnitude of gate potentials.
increases
decreases
remains constant
none of the above
FPGA is a
full-custom ASIC
semi-custom ASIC
programmable ASIC
structured ASIC
CLBs are used in
gate array design style
standard cell based design
Field programmable gate array layout
full custom design
Channelless Gate array is a sub-type of
FPGA
PLD
ASIC
Microprocessor
________is a programmable ASIC
Cell based ASIC
Full custom ASIC
Field programmable Gate array based ASIC
Structured Gate Array based ASIC
Compared to FPGA, ASIC takes _______ time to market.
short
medium
large
flexible
Logic Modules are used in ________FPGA
Altera
Actel
XIlinx
All of the above
Shannon's expansion theorem is applied to ________ logic function in _______ FPGAs
reduce,Altera
expand,Actel
expand,Altera
reduce,Actel
