WorksheetsSYSTEM DESIGN THROUGH VERILOG
Total questions: 20
Worksheet time: 13mins
What are the possible values of == operator
0,1
0,x
1,x
0,1,x
What is the time period of clock #10 clock = ~clock
10
20
.05
.1
wait statement is
edge sensitive bit
level sensitive
both
none
Asynchronous reset is
Clock dependent
Clock independent
Either
None
For describing circuits like flip flops _____________ statement is used
always
assign
initial
forever
Which construct is used to execute loop fixed number of times
while
forever
for
none
RTL stands for _____________.
resistor‐transfer logic
register‐transistor logic
register‐transfer logic
none of these
What will the following code segment generate on synthesis?
always @(posedge clock)
begin
data3 <= din;
data2 <= data3;
data1 <= data2;
data0 <= data1;
end
Four D flip-flops all fed with the data “din”.
A 4-bit shift register.
A 4-bit parallel-in parallel-out register.
None of these.
Which of the following loops are
supported by verilog?
if-else loop
for loop
while loop
All the above
Which level of abstraction level is available in Verilog but not in VHDL?
Behavioral level
Structural level
Dataflow level
Switch level
Variable and signal which will be updated first?
variable
signal
can't say
None of the above
The input and output ports should be declared inside the ________
Module
Case
wire
None of the above
Which of the following loops are
supported by verilog?
if-else loop
for loop
while loop
All the above
Which level of abstraction level is available in Verilog but not in VHDL?
Behavioral level
Structural level
Dataflow level
Switch level
Which logic level is not supported by
verilog?
U
X
Z
None of the above
Variable and signal which will be updated first?
variable
signal
can't say
None of the above
Which of the following is a difference between a Function and a Task?
A Function can call another function; a Task cannot
A Function cannot call a task; a Task can call another task
A Function has one or more inputs; a Task has no inputs
A Function argument may be an output; a Task’s argument may only be an input
In most synthesis tools, what will happen when a signal that is needed in a sensitivity list is not included?
An error will be generated and the code cannot be synthesized
A warning message will be generated and the code will be synthesized but the resulting netlist will not provide the desired results
The synthesis tool will ignore the sensitivity list since all objects that are read as part of a procedural assignment statement are considered to be sensitive
There will be no effect on the design and pre-synthesis simulation will be consistent with post-synthesis simulation
The keyword @posedge means
Transition from 0 to 1,x or z
Transition from x to 1
Transition from z to 1,x
All the above
Verilog may be written at the
Behavioral level
Structural level
dataflow level
All the above
