WorksheetsVLSI Quiz 2024-2025
Total questions: 17
Worksheet time: 9mins
Name
Class
Date
1.
Name
4 lines
2.
USN
4 lines
3.
1. The electrical equivalent component for a MOS structure is ________.
a)
resistor
b)
capacitor
c)
inductor
d)
switch
4.
2. The ID−VGS characteristics of a MOSFET in the saturation region is ______.
a)
linear
b)
quadratic
c)
logarithmic
d)
parabolic
5.
3. The CMOS inverter can be used as an amplifier when:
a)
NMOS operates in linear region and PMOS operates in saturation region
b)
NMOS operates in saturation region and PMOS operates in linear region
c)
Both NMOS and PMOS operates in linear region
d)
Both NMOS and PMOS operates in saturation region
6.
4. When the input of a CMOS inverter is equal to its switching threshold, the transistors are operating in:
a)
NMOS in cut-off and PMOS in saturation
b)
PMOS in cut-off and NMOS in saturation
c)
Both the transistors are in linear region
d)
Both the transistors are in saturation region
7.
5. Which of the following is false for a CMOS transmission gate?
a)
It has one NMOS and one PMOS connected in parallel.
b)
Control input is connected to gate of NMOS, and its complement is connected to gate of PMOS.
c)
It has one NMOS and one PMOS connected in series.
d)
It works as a controlled electric switch.
8.
6. The circuit employs pass transistor logic. All NMOS transistors are identical with threshold voltage of 0.6V. Ignoring the body effect, the output voltage at node S is ____. Consider VDD=5V.
a)
4.4V
b)
3.8V
c)
3.2V
d)
2.6V
9.
7. The overall power consumption of dynamic logic is _______ the power consumption of static CMOS logic.
a)
higher than
b)
smaller than
c)
equal to
d)
negligible, compared to
10.
8. One of the primary drawback of transmission gate register is _________.
a)
lower output swing
b)
high capacitive load presented to the clock signal
c)
high capacitive load presented to the input signal
d)
lower output drive capability
11.
9. Dynamic logic typically requires ______ transistors, whereas typical static CMOS logic uses 2N transistors.
a)
N
b)
N+1
c)
N+2
d)
2N
12.
10. Ratioed logic typically requires ______ transistors, whereas typical un-ratioed CMOS logic uses 2N transistors.
a)
N
b)
N+1
c)
N2
d)
2N
13.
11. Source and drain in nMOS device are isolated by
a)
a) a single diode
b)
b) two diodes
c)
c) three diodes
d)
d) four diode
14.
12. MOS transistor structure is
a)
a) symmetrical
b)
b) non symmetrical
c)
c) semi symmetrical
d)
d) pseudo symmetrical
15.
13. C2MOS latch is insensitive to clock overlaps because:
a)
Clock is not used.
b)
Either of clock or clock bar is used, but not both.
c)
Those overlaps activates either the pull-up or the pull-down networks of the latches, but never both of them simultaneously.
d)
It is level triggered.
16.
14. A ______ is a level sensitive device while a ______ is an edge triggered device.
a)
register; latch
b)
latch; register
c)
inverter; latch
d)
D-flip flop; inverter
17.
15. In linear region, a MOSFET works as a _______, while in saturation region it works as a ______.
a)
current source; resistor
b)
resistor; current source
c)
resistor; inductor
d)
capacitor; inductor
100 %
