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WorksheetsBoolean Algebra and Logic Circuits
Total questions: 70
Worksheet time: 2hrs 48mins
Which of the following architectures consists of a single instruction stream and a single data stream?
A. SIMD
B. MISD
C. SISD
D. MIMD
Which architecture processes multiple data elements with a single instruction?
A. SISD
B. SIMD
C. MIMD
D. MISD
In which architecture do multiple processors execute different instructions on different data?
A. MIMD
B. MISD
C. SISD
D. SIMD
Which of the following architectures is rarely used and mainly theoretical?
A. SISD
B. MISD
C. SIMD
D. MIMD
Which architecture is best suited for fault-tolerant systems using redundant processing?
A. SIMD
B. SISD
C. MISD
D. MIMD
Massively parallel computers are best characterized by:
A. One processor executing many instructions
B. Many processors working on the same task simultaneously
C. Using only SISD architecture
D. Executing a single thread at a time
Which of the following is a major benefit of massively parallel computers?
A. Simplified programming
B. High energy consumption
C. Speedup in data processing
D. Cost-effectiveness per core
A virtual machine (VM) is best described as:
A. A hardware processor
B. A physical server
C. A software emulation of a physical computer
D. A logic circuit
One advantage of using a virtual machine is:
A. Increased hardware cost
B. Platform dependency
C. Need for physical relocation
D. Ability to run multiple OS environments
Which of the following is a limitation of virtual machines?
A. Slower performance compared to native execution
B. Poor compatibility with physical hardware
C. No support for multitasking
D. Cannot install applications
What is the sum output of a half adder with inputs A=1 and B=0?
A. 0
B. 1
C. 2
D. Undefined
Which logic gates are used in a half adder?
A. OR and NOT
B. AND and XOR
C. NAND and NOR
D. XOR and NOR
How many inputs does a full adder have?
A. 2
B. 3
C. 4
D. 1
What is the carry-out of a full adder with inputs A=1, B=1, Cin=1?
A. 0
B. 1
C. Undefined
D. 2
Which component is NOT part of a full adder design?
A. XOR gates
B. AND gates
C. OR gates
D. NOT gates
A flip-flop is a type of:
A. Combinational circuit
B. Multiplexer
C. Sequential circuit
D. Encoder
What is the output of an SR flip-flop when S=1 and R=0?
A. Q=0, Q̅=1
B. Q=1, Q̅=0
C. Invalid
D. Toggle
What condition makes the output of an SR flip-flop invalid?
A. S=0, R=1
B. S=1, R=0
C. S=1, R=1
D. S=0, R=0
Which flip-flop type avoids the invalid state of the SR flip-flop?
A. T Flip-Flop
B. D Flip-Flop
C. JK Flip-Flop
D. Master-Slave
A JK flip-flop toggles its output when:
A. J=1, K=1
B. J=0, K=0
C. J=1, K=0
D. J=0, K=1
Which Boolean law states that A + 0 = A?
A. Complement Law
B. Identity Law
C. Domination Law
D. Inverse Law
Simplify the Boolean expression A + AB.
A. AB
B. A
C. B
D. A + B
Which of the following is equivalent to A(A + B)?
A. AB
B. A + B
C. A
D. B
DeMorgan’s theorem for (AB)’ is:
A. A’B’
B. A’ + B’
C. A + B
D. (A + B)’
What is the purpose of a Karnaugh map?
A. Increase propagation delay
B. Minimize Boolean expressions
C. Convert binary to decimal
D. Generate truth tables
How many cells are in a 3-variable K-map?
A. 4
B. 6
C. 8
D. 16
What is a group of 4 adjacent 1s in a K-map called?
A. Octet
B. Pair
C. Quad
D. Unit
Which of the following is a valid grouping in a K-map?
A. Diagonal group of 1s
B. 3 adjacent 1s
C. 5 adjacent 1s
D. Group of 2^n 1s
Which of the following helps reduce the number of logic gates in a circuit?
A. Creating truth tables
B. Using flip-flops
C. Simplifying expressions with K-map
D. Adding redundant logic
A full adder differs from a half adder because it includes:
a) An additional input for carry-in
b) Only two inputs (A and B)
c) No carry output
d) Only NAND gates
In a half adder, the sum output is given by:
a) A AND B
b) A OR B
c) A XOR B
d) A NAND B
A key benefit of using a virtual machine (VM) is:
a) Reduced hardware costs due to resource sharing
b) Higher single-threaded performance
c) Elimination of all security risks
d) No need for an operating system
Which architecture allows multiple instructions to operate on a single data stream?
a) SISD
b) SIMD
c) MISD
d) MIMD
When grouping cells in a K-map, which rule must be followed?
a) Groups must always be square-shaped
b) Groups must contain only adjacent '1's (including wrap-around)
c) Groups must include at least one '0'
d) Groups must be in a straight line only
A half adder can be constructed using which gates?
a) One AND and one OR gate
b) One XOR and one AND gate
c) One NAND and one NOR gate
d) One NOT and one OR gate
A full adder requires how many inputs?
a) 2 (A and B)
b) 3 (A, B, and Carry-in)
c) 4 (A, B, Carry-in, and Carry-out)
d) 1 (A only)
In an SR flip-flop, what happens when S=1 and R=1?
a) The output toggles
b) The output becomes 0
c) The output becomes 1
d) The state is invalid/forbidden
A JK flip-flop eliminates the forbidden state of an SR flip-flop by:
a) Adding a clock input
b) Making J=1 and K=1 toggle the output
c) Removing the set and reset inputs
d) Using only NAND gates
Which of the following is the correct truth table for an AND gate with two inputs (A and B)?
A = 0, B = 0 → Output = 1
A = 0, B = 1 → Output = 1
A = 1, B = 0 → Output = 1
A = 1, B = 1 → Output = 1
What is the output of an OR gate if both inputs are 1?
1
0
Depends on the circuit
Undefined
A NOT gate produces what kind of output?
The inverse of the input
The sum of the inputs
The product of the inputs
A constant 0
What is the output of an XOR gate when both inputs are the same?
0
1
It depends on the number of inputs
Undefined
What does a half adder circuit do?
Adds two binary digits and produces a sum and a carry output
Subtracts two binary numbers
Adds multiple binary numbers at once
Performs logical AND and OR operations
Which two logic gates are required to construct a half adder?
XOR and AND
OR and AND
NOR and NAND
XOR and NOT
Which additional gate(s) are required to build a full adder in addition to those in a half adder?
XOR and OR
NOR and XOR
NAND and NOR
NOT and AND
What is the main purpose of a flip-flop in digital circuits?
To store a single bit of data
To add two binary numbers
To act as a counter
To generate random numbers
Which of the following is a type of flip-flop?
SR flip-flop
AND flip-flop
XOR flip-flop
NOR flip-flop
Which inputs does an SR flip-flop have?
Set (S) and Reset (R)
Clock (C) and Data (D)
Enable (E) and Reset (R)
Input (I) and Output (O)
What is a major problem with an SR flip-flop?
The output is unpredictable when both inputs are 1.
It cannot store a binary value.
It has no clock input.
It does not allow toggling of states.
How does a JK flip-flop differ from an SR flip-flop?
It resolves the issue of the SR flip-flop’s indeterminate state.
It cannot store binary data.
It is only used for multiplication.
It requires more inputs than an SR flip-flop.
What is the Boolean expression for a NAND gate?
NOT(A • B)
NOT(A + B)
A • B
NOT(A) + NOT(B)
Which Boolean expression represents an OR gate?
A + B
A • B
NOT(A) • NOT(B)
NOT(A + B)
Which logic gate produces an output of 1 only when all inputs are 0?
NOR
AND
XOR
NAND
What is the main advantage of using a Karnaugh Map?
It simplifies Boolean expressions systematically.
It increases the number of logic gates needed.
It converts logic gates into flip-flops.
It performs binary addition automatically.
Which of the following statements accurately represents the two BEST methods of logic circuit simplification?
Actual circuit trial and error evaluation and waveform analysis
Karnaugh mapping and circuit waveform analysis
Boolean algebra and Karnaugh mapping
Boolean algebra and actual circuit trial and error evaluation
What is the simplified expression?
B' + D
B'D
B + D'
AB + CD
Find sop expression for the K-MAP
X'Y' + W'
XY + YW
XY' + W'
X'Y + W
The circuit shown in figure below generates the function of
X xor Y
XY' + X'Y
XY'
XY' + XY + XY'
0
Consider the given K-map What would be the simplified expression?
b'D + Ab' + c'D
Bd'+ Ad' + c'D
b'd' + BD + A
c'D + ABc+ aBC + AD
Consider the given K-map What would be the simplified expression?
b'D + Ab' + c'D
Bd'+ Ad' + c'D
b'd' + BD + A
c'D + ABc+ aBC + AD
Write the SOP.
C
C'
A
B
Write the SOP.
A'C'
B'C
A'C
AC
Write the SOP.
A'C'+AC
AC
BC+B'C'
C'A+A
Write the SOP.
A'C+B'C
A'C+BC
AC+B'C
AC+BC
Write the SOP
B'C+A'C
B'C+A'C+AC'
BC+AC
B'C+AC+AC'
Write the SOP.
A'B'C'D+A'BC+BCD'
A'B'C'D+ABC+BCD'
A'B'C'D+A'BC+BCD
A'B'C'D+A'BC
Write the SOP.
RT + RS
R'T + RS
R'T + RS'
RTS
