The maximum amount of data that can be transferred.

The speed at which data can be transferred.

The delay before the data transfer begins.

The frequency of data refreshing.

The amount of data transferred per cycle.

The speed at which data can be transferred, usually measured in MHz or GHz.

The time it takes for memory to boot up.

The number of errors in data transfer.

By reducing the clock speed.

By allowing for the continuous transfer of data, reducing overhead.

By increasing latency.

By decreasing bandwidth.

RAMBUS transfers data in single bits, allowing for lower bandwidth.

RAMBUS transfers data in large blocks, allowing for higher bandwidth and faster data transfer.

RAMBUS is more volatile than SDRAM.

RAMBUS requires less power than SDRAM.

Blocks of data.

Single bits.

Packets.

Burst mode.

DRAM

SDRAM

RAMBUS

SRAM

Primary memory is non-volatile, secondary is volatile.

Primary memory is temporary and faster, secondary is long-term and slower.

Primary memory is for storage, secondary is for processing.

Primary memory is external, secondary is internal.

It acts as a permanent storage for all data.

It stores frequently accessed data to reduce the time needed to fetch data from slower main memory.

It directly connects the CPU to external devices.

It manages the power supply to the CPU.

It can only transfer data on the rising edge of the clock cycle.

It can transfer data on both the rising and falling edges of the clock cycle.

It is slower than traditional SDRAM.

It uses single-bit transfers.

Permanent storage of operating system files.

Temporary storage for data actively being used by the CPU.

Long-term archival of user documents.

Storing firmware for hardware components.

Its use of capacitors that require constant refreshing.

Its ability to store data in flip-flops without needing refreshing.

Its higher density, allowing more data in a smaller space.

Its lower power consumption.

Fully charged.

Partially charged.

Not charged.

Overcharged.

Faster access speeds.

Higher data density.

Data retention without power.

Lower manufacturing cost.

ROM

Flash Memory

Hard Drives

DRAM

To increase the storage capacity.

To prevent the loss of data due to charge leakage.

To speed up data access.

To reduce power consumption.

Shift registers are used for permanent storage.

Shift registers store data in a serial manner and are used for temporary storage or data conversion.

Shift registers are non-volatile.

Shift registers do not hold single bits of data.

A type of capacitor.

A circuit made up of transistors that stores a bit of data.

A mechanism for refreshing memory.

A non-volatile storage unit.

It provides permanent storage for all programs.

It offers fast, temporary storage for data the CPU needs immediately.

It acts as a backup for the hard drive.

It controls external peripherals.

The use of transistors.

The natural leakage of charge from capacitors.

The need for high clock speeds.

The physical size of the memory cells.

To find the lowest possible value for a given function.

To identify the solution that yields the greatest benefit or output.

To reduce the number of variables in the problem.

To simplify the problem to a manageable size.

The final answer to a mathematical equation.

A candidate approach or outcome to a problem that may have an associated cost or value.

A method for debugging algorithms.

A theoretical concept with no practical application.

It is always the most efficient and cost-effective option.

It is a valid and reasonable solution that meets requirements, though not necessarily optimal.

It is a solution that can only be found using brute force.

It is a solution that is impossible to implement in the real world.

They are too complex to implement for most problems.

They always find the global optimum, making them slow.

They make locally optimal choices that do not always lead to a globally optimal solution.

They require extensive memory to store subproblem solutions.

For problems that can be solved by making a series of locally optimal choices.

For problems that involve checking every possible solution.

For problems that can be broken down into smaller, overlapping subproblems.

For problems with no clear mathematical structure.

The theoretical cost calculated by the cost function.

The real-world cost incurred during the implementation and execution of a solution.

The minimum possible cost achievable for any solution.

The cost associated with developing the optimization model.

Brute Force

Dijkstra's Algorithm

Simulated Annealing

Dynamic Programming

Minimizing seeks the lowest value, while maximizing seeks the highest value.

Minimizing applies only to financial costs, maximizing to profits.

Minimizing is a faster process than maximizing.

There is no fundamental difference; they are interchangeable terms.

The number of nodes visited.

The sum of the weights or costs of the edges along a specific path.

The time taken to compute the path.

The total number of possible paths.

It is the easiest solution to implement.

It is the best possible solution, outperforming all others in terms of the objective.

It is a solution that satisfies only some of the problem's constraints.

It is a solution found by a greedy algorithm.

To identify the specific word within a cache line.

To differentiate between different blocks of memory.

To specify which cache line the memory block will go into.

To determine the size of the cache.

When the requested data is not found in the cache.

When the requested data is found in the cache.

When the cache memory is full.

When the CPU accesses main memory directly.

Conflict miss

Capacity miss

Compulsory miss

Coherence miss

Its high cost.

Its complexity in implementation.

Its susceptibility to cache conflicts.

Its slow access time compared to main memory.

It eliminates all cache misses.

It allows any block of memory to be stored in any cache line.

It divides the cache into sets, allowing a memory block to be placed in any cache line within a set, reducing conflicts.

It only uses a single cache line for all memory blocks.

To identify the cache line.

To identify the specific word within a cache line.

To identify the memory block.

To determine the overall memory address size.

To specify the cache line.

To identify the specific word within a cache line.

To identify which block of memory is being referenced.

To indicate the size of the memory block.

When the cache is too small to hold all the needed data.

When two different memory blocks are mapped to the same cache line.

When data is accessed for the first time.

When there is an error in the cache hardware.

The percentage of cache accesses that result in a miss.

The percentage of cache accesses that result in a hit.

The total number of cache accesses per second.

The speed at which data is transferred from main memory.

A miss that occurs due to cache conflicts.

A miss that occurs when the cache is too small to hold all the needed data.

A miss that occurs the first time data is accessed.

A miss that occurs due to a faulty memory module.

To provide power to components.

To manage communication and direct data flow between components.

To store data permanently.

To perform arithmetic operations.

When CS is inactive (logic high).

When CS is active (usually logic low).

When the RESET signal is active.

When the Clock signal is high.

To provide a constant voltage supply.

To synchronize operations and determine the data processing rate.

To generate random numbers.

To store temporary data.

The processor immediately stops all operations.

The processor pauses its current task, handles the interrupt, and then resumes.

The system reboots.

The memory is cleared.

To prevent any data from being written to memory.

To ensure that a critical operation is not interrupted by other processors.

To lock the system for security reasons.

To increase the speed of data transfer.

By using a single clock signal for all chips.

By activating the Chip Select (CS) signal for the desired chip.

By resetting all other chips.

By using the Interrupt signal.

CS manages data flow, RESET manages power.

CS enables/disables a chip, RESET initializes a chip or system to a known state.

CS is for input, RESET is for output.

CS is for software, RESET is for hardware.

It speeds up data processing.

It brings the system to a predefined, known state after errors or power-up.

It increases memory capacity.

It prevents external interference.

The amount of data stored in memory.

The rate at which data is processed and operations are synchronized.

The number of peripherals connected to the system.

The voltage levels in the circuit.

It could lead to increased system performance.

It could cause delays, resource contention, or deadlocks.

It could reduce power consumption.

It could automatically correct all system errors.

To link two tables together.

To uniquely identify a record in a table, though it may contain redundant attributes.

To ensure that all values in a column are distinct.

To provide a backup for the primary key.

A key that can have NULL values.

A minimal super key with no redundant attributes.

A key used to link two tables.

A key that is automatically generated by the database.

It can have NULL values.

It is chosen from the candidate keys to uniquely identify each record and cannot be NULL.

It is used only for sorting data.

It is optional for every table.

To uniquely identify records within its own table.

To establish a link between two tables by referencing the primary key of another table.

To ensure that all values in a column are distinct.

To speed up data insertion.

A key that consists of a single column.

A key that consists of two or more columns to uniquely identify a record.

A key that is automatically generated by the database.

A key that is used for encryption.

A Primary Key can have NULL values, while a Unique Key cannot.

A Primary Key cannot have NULL values, while a Unique Key can (in most databases).

A table can have multiple Primary Keys, but only one Unique Key.

A Primary Key is used for linking tables, while a Unique Key is not.

One

Two

As many as there are columns.

Unlimited

The table will be more secure.

The table may allow duplicate records and have data integrity issues.

The table will be read-only.

The database will automatically create a composite key.

Primary Key

Super Key

Foreign Key

C

Primary Key

Super Key

Foreign Key

Candidate Key

A super key with the maximum number of attributes.

A candidate key.

A candidate key.

A foreign key.

A composite key.

DML

DQL

DDL

TCL

To add new rows to a table.

To modify the structure of an existing database object.

To delete data from a table.

To retrieve data from a table.

UPDATE

SELECT

INSERT

DELETE

To define database objects.

To manipulate data within tables.

To query and retrieve data from the database.

To manage transactions.

ROLLBACK

SAVEPOINT

COMMIT

RELEASE

Deletes specific rows from a table.

Removes all records from a table, but keeps the table structure.

Deletes the entire table from the database.

Modifies existing data in a table.

REVOKE

DENY

GRANT

ALLOW

`DELETE` is faster than `TRUNCATE`.

`DELETE` can be rolled back, `TRUNCATE` cannot.

`DELETE` removes the table structure, `TRUNCATE` only removes data.

`DELETE` is DDL, `TRUNCATE` is DML.

INSERT

UPDATE

SELECT

DELETE

To commit the transaction.

To undo all changes in the transaction.

To set a point within a transaction to which you can later roll back.

To create a new transaction.

It is non-volatile and stores data permanently.

It is volatile and provides temporary storage for active data.

It is slower than secondary memory.

It is used for long-term data archiving.

By using a slower clock speed.

By transferring data in larger blocks.

By reducing the number of data lines.

By requiring more frequent refreshing.

It consumes less power.

It can transfer data twice per clock cycle.

It has a smaller physical footprint.

It is non-volatile.

Bandwidth

Throughput

Latency

Clock Speed

To reduce the clock speed.

To allow faster data transfer to and from memory.

To increase the physical size of the memory modules.

To make the memory non-volatile.

RAM

Cache memory

Secondary memory

Registers

To store all data permanently.

To speed up access to frequently used data by the CPU.

To manage network connections.

To provide backup for main memory.

By operating independently of the system clock.

By synchronizing its operations with the system clock.

By using capacitors for data storage.

By transferring data one bit at a time.

Bit-based transfers are faster.

Block-based transfers move more data at once, increasing efficiency.

Bit-based transfers are used in networking, block-based in memory.

There is no significant difference in efficiency.

It reduces the amount of data transferred.

It allows for continuous data transfer, maximizing clock cycle use.

It increases the latency of data access.

It makes the memory volatile.

RAM

CPU Cache

SSD (Solid State Drive)

CPU Registers

They are inversely proportional.

Bandwidth is the maximum data transfer rate.

Bandwidth only applies to network connections.

Data transfer rate is always higher than bandwidth.

It decreases the data transfer rate.

It increases the data transfer rate.

It increases latency.

It makes the memory less reliable.

To increase the physical size of the computer.

To provide different levels of speed, cost, and storage capacity for various needs.

To simplify the memory management unit.

To reduce the overall power consumption of the system.

SRAM

DRAM

RAMBUS

ROM

It transfers data in large blocks.

It transfers data one bit at a time.

It transfers data on both edges of the clock cycle.

It is asynchronous.

By using a wider bus.

By transferring data on both the rising and falling edges of the clock cycle.

By increasing the latency.

By reducing the clock speed.

To store all user data permanently.

To bridge the speed gap between the CPU and main memory.

To provide a backup for the operating system.

To manage network traffic.

Primary memory

Secondary memory

Tertiary memory

Cache memory

Single-bit data transfer.

Packet-based data transfer.

Block-based data transfer.

Asynchronous operation.