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Computer Architecture Quiz 5

Total questions: 43

Worksheet time: 22mins

Name
Class
Date
1.

Indexing performed after the indirection is

a)

relative addressing

b)

autoindexing

c)

postindexing

d)

preindexing

2.

The I/O function includes a ______requirement to coordinate the flow of traffic between internal resources and external devices

a)

cycle

b)

status reporting

c)

control and timing

d)

data

3.

An I/O module must recognize one unique address for each peripheral it controls.

a)

True

b)

False

4.

The method of calculating the EA is the same for both base-register addressing and indexing.

a)

True

b)

False

5.

Both batch multiprogramming and time sharing use multiprogramming.

a)

True

b)

False

6.

A common example of system interconnection is by means of a____

a)

register

b)

system bus

c)

data transport

d)

control device

7.

The ENIAC is an example of a_____ generation computer

a)

first

b)

second

c)

third

d)

fourth

8.

INT 21h/AH=1 is

a)

write character from standard input, entry is stored in AL.

b)

read character from standard input, with echo, result is stored in AL.

c)

write character from standard input, entry is stored in AH.

d)

read character from standard input, with echo, result is stored in AH.

9.

A ____disk is permanently mounted in the disk drive, such as the hard disk in a personal computer.

a)

nonremovable

b)

movable-head

c)

double sided

d)

removable

10.

The set of all the tracks in the same relative position on the platter is referred to as a _________

a)

floppy disk

b)

single-sided disk

c)

sector

d)

cylinder

11.

Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage of Advances in device performance

a)

True

b)

False

12.

The number of bits used to represent various data types is an example of an architectural attribute.

a)

True

b)

False

13.

Program execution consists of repeating the process of instruction fetch and instruction execution

a)

True

b)

False

14.

_____are a set of storage locations

a)

Processors

b)

PSWs

c)

Registers

d)

Control units

15.

Scheduling and memory management are the two os functions that are most relevant to the study of computer organization and architecture

a)

True

b)

False

16.

Condition codes facilitate multiway branches

a)

True

b)

False

17.

Which of the following interrelated factors go into determining the use of the addressing bits?

a)

number of operands

b)

number of register sets

c)

address range

d)

all of the above

18.

A characteristic of ROM is that it is volatile.

a)

True

b)

False

19.

_____is the standardized scheme for multiple disk database design.

a)

RAID

b)

CAV

c)

CLV

d)

SSD

20.

The use of multiple processors on the same chip is referred to as_______ and provides the potential to increase performance without increasing the clock rate

a)

multicore

b)

GPU

c)

data channels

d)

MPC

21.

RAID level 0 is not a true member of the RAID family because it does not include redundancy to improve performance

a)

True

b)

False

22.

The ___________cycle occurs at the beginning of each instruction cycle and causes an instruction to be fetched from memory

a)

execute

b)

indirect

c)

fetch

d)

. interrupt

23.

es not include redundancy to improve performance

a)

True

b)

False

24.

The ___________cycle occurs at the beginning of each instruction cycle and causes an instruction to be fetched From memory

a)

execute

b)

indirect

c)

fetch

d)

interrupt

25.

In a volatile memory, information decays naturally or is lost when electrical power is switched off.

a)

True

b)

False

26.

Register addressing is similar to direct addressing with the only difference being that the address field refers to a register rather than a main memory address.

a)

True

b)

False

27.

Semiconductor memory comes in packaged chips.

a)

True

b)

False

28.

It is possible to improve pipeline performance by automatically rearranging instructions within a program so That branch instructions occur later than actually desired

a)

True

b)

False

29.

A computer has memory of 256k words, how many bits are required to specify the address part?

a)

16 bits

b)

12 bits

c)

8 bits

d)

18 bits

e)

10 bits

30.

A sequence of codes or instructions is called

a)

software

b)

memory

c)

an interconnect

d)

a register

31.

With a batch operating system the user does not have direct access to the processor.

a)

True

b)

False

32.

The two traditional forms of RAM used in computers are DRAM and SRAM

a)

True

b)

False

33.

The correspondence between the main memory blocks and those in the cache IS specified by

a)

Mapping function

b)

Replacement algorithm

c)

Hit rate

d)

Miss penalty

e)

Segment function

34.

Microprogramming eases the task of designing and implementing the control unit and provides support for the Family concept

a)

True

b)

False

35.

A_______ hazard occurs when there is a conflict in the access of an operand location

a)

resource

b)

data

c)

structural

d)

control

36.

The most common means of computer/user interaction is a

a)

keyboard/monitor

b)

mouse/printer

c)

modem/printer

d)

monitor/printer

37.

The____contains the 8-bit opcode instruction being executed

a)

memory buffer register

b)

instruction buffer register

c)

instruction register

d)

memory address register

38.

The memory transfer rate has not kept up with increases in processor speed

a)

True

b)

False

39.

The end user IS concerned mainly with the computer’s architecture

a)

True

b)

False

40.

The performance of the cache memory is measured in terms of a quantity called____

a)

Initialization Ratio

b)

Address Ratio

c)

Hit Ratio

d)

Instruction Ratio

e)

Miss Ratio

41.

For internal memory, the____ is equal to the number of electrical lines into and out of the memory Module

a)

access time

b)

unit of transfer

c)

capacity

d)

memory ratio

42.

A_______ is HO electronic circuit that produces 1911 output signal that is и simple Doolware operation on is input signals

a)

gate

b)

decoder

c)

counter

d)

flip-flop

43.

The only form of adda essing for branch instructions is _____addressing

a)

register

b)

Relative

c)

base

d)

immediate