WorksheetsComputer Architecture Quiz 7
Total questions: 42
Worksheet time: 24mins
The only form of addressing for branch instructions is ____addressing.
register
relative
base
immediate
A_______is an electronic circuit that produces an output signal that is a simple Boolean operation on its input signals
gate
decoder
counter
flip-flop
Choose the most four basic functions of a computer.
Moving data, storing data, processing data, controlling.
Supporting operating system, accessing hard disks, supporting network connections, supporting HDMI ports.
Reading disks, accessing network resources.
Reading data from keyboard, printing data to monitor, allowing network connections.
___refers to the operational units and their interconnections that realize the architectural specifications.
Computer architecture
Computer function
Computer organization
Instruction set architecture
What is the most important function of the control unit (CU)?
It manages the order of running instructions.
It will read and process data from main memory.
It directs the operation of the other CPU components.
It will read instructions from main memory then decoding them.
What is Memory Address Register (MAR)?
Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit.
Employed to hold temporarily the righthand instruction from a word in memory.
Contains the address in memory of the word to be written from or read into the MBR.
Contains the address of the next instruction pair to be fetched from memory
What is false about the von Neumann architecture?
Data and instructions are stored in a single read-write memory.
The contents of this memory are addressable by location, without regard to the type of data contained there.
Execution occurs in a sequential fashion (unless explicitly modified) from one instruction to the next.
Data is stored in main memory and instructions are stored in cache memory
What is the maximum addressable memory of a 32-bit microprocessor with 24-bit address?
16 GB
16 MB
16 Gbits
16 Mbits
What is the special feature of Memory Cache?
Allows faster access than DRAM memory
Memory cache is outboard storage memory
Allows faster access than CPU registers
Fixed memory – Read Only Memory
Has a larger capacity than HDD
In the direct mapping method from 256MB main memory with 512KB cache, what is the number of bits for the TAG element in the address?
6
7
8
9
A byte addressable microprocessor has 24 bit address. What is maximum memory capacity?
4 MegaByte
8 MegaByte
16 MegaByte
32 MegaByte
In error correcting code (single ECC), how many bits are used to correct one bit in 8-bit data?
4.
5
6
7
Which RAID level uses striping technique with a minimum of 3 disks and provides fault tolerance through the use of parity bit?
RAID 0
RAID 1
RAID 2
RAID 3
In terms of performance, what is the main advantage of a solid state drive over a magnetic disk?
A solid state drive has faster access time, lower latency, and higher reliability
A solid state drive has larger capacity, lower power consumption, and lower cost
A solid state drive has better compatibility, longer lifespan, and higher security
A solid state drive has none of the mentioned advantages over a magnetic disk
Consider the expression: NOT(A + B) = ? Apply DeMorgan’s Theorem to replace at “?”
NOT A AND NOT B
NOT A OR NOT B
NOT A AND B
A OR NOT B
(1) An I/O module must recognize one unique address for each peripheral it controls. (2) I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on mainframes.The statement (1) is and (2) is
true, false
true, true
false, true
false, false
What is an interrupt vector?
Part of memory which contains the addresses of interrupt handlers
A signal an I/O device sends to CPU
A signal an I/O software sends to CPU
None of the mentioned
If the operation involves reference to an operand in memory or available via I/O, then determine the address of the operand.
Operand fetch
Data operation
Operand store
Operand address calculation
What is result of 10100101 xor 11001001?
11101101
10000001
01101100
10101100
What is result left rotate of 10110101 by 2 bit?
01101011
10101101
01101101
11010110
11010100
The effective address of Register indirect addressing mode is
EA = R
EA = (R)
EA = (R)+A
EA = (R)+(A)
What is the main difference between x86 and ARM instruction formats?
What is the main difference between x86 and ARM instruction formats?
x86 instructions are variable in length, while ARM instructions are fixed
x86 instructions are fixed in length, while ARM instructions are variable
Both x86 and ARM instructions are fixed in length
Both x86 and ARM instructions are variable in length
What is the primary purpose of the “Fetch instruction” phase in the operation of a processor?
To read an instruction from memory
To interpret the instruction
To perform arithmetic operations on data
To write data to memory
Control and status registers are used by which entities to control the operation of the processor?
Privileged, operating system programs
Machine or assembly language programmers
External I/O devices
Main memory modules
Which of the following statement is correct in the context of Instruction Pipelining?
Instruction Pipelining reduces the efficiency of instruction execution by introducing delays and dependencies between instructions
Instruction Pipelining is only effective for specific types of instructions and has no impact on the overall efficiency of instruction execution
Instruction Pipelining enhances efficiency by enabling simultaneous execution of multiple instructions in different stages, boosting overall throughput
Instruction Pipelining improves efficiency by processing multiple instructions simultaneously, reducing execution time. However, it can face challenges like hazards, introducing delays and impacting overall performance
“Multiple processors share a single memory or pool of memory by means of a shared bus or other interconnection mechanism; a distinguishing feature is that the memory access time to any region of memory is approximately the same for each processor”. Which concept does the statement belong to?
Symmetric multiprocessor (SMP)
Nonuniform memory access (NUMA)
Cluster
Single instruction, multiple data (SIMD)
Suppose sellers of perfume are required to send $1.00 to the government for every bottle of perfume they sell. Further, suppose this tax causes the price paid by buyers of perfume to rise by $0.60 per bottle. Which of the following statements is correct?
Sixty percent of the burden of the tax falls on sellers.
This tax causes the demand curve for perfume to shift downward by $1.00 at each quantity of perfume.
The effective price received by sellers is $0.40 per bottle less than it was before the tax.
All of the above are correct
Alicia is a vegetarian, so she does not eat beef. That is, beef provides no additional utility to Alicia. She loves potatoes, however. If we illustrate Alicia’s indifference curves by drawing beef on the horizontal axis and potatoes on the vertical axes, her indifference curves will:
slope downward
Be vertical straight lines
Slope upward
Be horizontal straight lines
If the income effect cancels the substitution effect, we know that the good in question is a(n):
complementary good
Inferior good
Luxury good
Normal good
The I/O technique where the CPU busy-waits for I/O completion is called:
Programmed I/O or DMA
Interrupt-Driven I/O
Direct Memory Access (DMA)
Programmed I/O
What distinguishes Interrupt-Driven I/O from DMA?
Interrupt-Driven I/O involves the CPU in every transfer; DMA bypasses the CPU.
Interrupt-Driven I/O requires special hardware; DMA does not.
Interrupt-Driven I/O is for small transfers; DMA is for large transfers.
All of the mentioned.
Which method maps logical addresses of variable length onto physical memory?
Paging
Overlays
Segmentation
Paging with segmentation
What is the result of a logical right shift of 10110000 by 2 bits?
00101100
10101100
10001100
00110000
In SuperScalar architecture, the primary goal of concurrent processing is to:
Increase CPU frequency.
Execute multiple instructions per cycle.
Reduce CPU size.
Increase core count.
Multiple functional units, each pipelined, describe which architecture?
Scalar
Superpipelined
Superscalar
Vector
Performs the computer’s data processing function:
Arithmetic and Logic Unit (ALU)
Control Unit
CPU Interconnection
Registers
Consider an expression: 1000 0000 OR 1111 1010. What is the result?
1000 0000
1111 1010
1001 1010
1001 0101
What is the benefit of cache memory in terms of computer performance?
It reduces the computer’s power consumption.
It speeds up data access and improves system performance.
It increases the storage capacity of the computer.
It serves as a backup storage for critical files.
The hardware mechanism for device notification is called:
Polling
Interrupt
Driver
Controlling
Which concept involves replicating register banks to share pipeline resources among threads?
Pipelining
Superscalar
Simultaneous multithreading
Superpipelining
How many general-purpose registers are there in Intel 80386—Pentium 4?
8
16
4
12
