WorksheetsComputer Architecture 1-4 Quiz
Total questions: 40
Worksheet time: 20mins
For internal memory, the __________ is equal to the number of electrical lines into and out of the memory module.
capacity
access time
memory ratio
unit of transfer
One increment, or pulse, of the system clock is referred to as a _________.
clock rate
clock tick
cycle time
cycle speed
The __________ moves data between the computer and its external environment.
I/O
register
CPU interconnection
data transport
A line includes a _________ that identifies which particular block is currently being stored.
cache
locality
tag
hit
A common example of system interconnection is by means of a __________.
data transport
system bus
register
control device
The data lines provide a path for moving data among system modules and are collectively called the _________.
system bus
control bus
address bus
data bus
The von Neumann architecture is based on which concept?
the contents of this memory are addressable by location
data and instructions are stored in a single read-write memory
all of the above
execution occurs in a sequential fashion
Internal memory capacity is typically expressed in terms of _________.
hertz
LOR
nanos
bytes
The Pentium 4 _________ component executes micro-operations, fetching the required data from the L1 data cache and temporarily storing results in registers.
out-of-order execution
fetch/decode unit
memory subsystem
execution unit
_________ provide storage internal to the CPU.
Control units
Main memory
ALUs
Registers
In two’s complement addition, if there is a final carry after the left most column addition, _______.
add it to the right most column
add it to the left most column
discard it
increase the bit length
When data are moved over longer distances, to or from a remote device, the process is known as __________.
structuring
registering
data communications
data transport
The interconnection structure must support which transfer?
processor to memory
memory to processor
I/O to or from memory
all of the above
The __________ defines the third generation of computers.
transistor
integrated circuit
vacuum tube
VLSI
The _______ method of integer representation is the most common method for storing integers in computer memory.
sign-and-magnitude
one’s complement
two’s complement
unsigned integers
It is aNo _________ design issue whether a computer will have a multiply instruction.
organizational
architectural
elementary
memory
Individual blocks or records have a unique address based on physical location with __________.
sequential access
physical access
direct access
associative access
The use of multiple processors on the same chip is referred to as __________ and provides the potential to increase performance without increasing the clock rate.
multicore
MPC
GPU
data channels
A __________ is the high-level set of rules for exchanging packets of data between devices.
bus
packet
QPI
protocol
The Electronic Numerical Integrator and Computer project was a response to U.S. needs during _________.
the French-American War
World War II
the Civil War
World War I
A sequence of codes or instructions is called __________.
memory
a register
software
an interconnect
A bus that connects major computer components (processor, memory, I/O) is called a __________.
control bus
system bus
address bus
data bus
During the _________ the opcode of the next instruction is loaded into the IR and the address portion is loaded into the MAR.
instruction cycle
clock cycle
fetch cycle
execute cycle
A logical cache stores data using __________.
random addresses
physical addresses
virtual addresses
none of the above
__________ is the simplest mapping technique and maps each block of main memory into only one possible cache line.
None of the above
Set associative mapping
Direct mapping
Associative mapping
The _______ is a computer subsystem that performs operations on data.
I/O hardware
CPU
bus subsystem
memory
In reference to access time to a two-level memory, a _________ occurs if an accessed word is not found in the faster memory.
line
miss
tag
hit
The __________ interprets the instructions in memory and causes them to be executed.
I/O
arithmetic and logic unit
main memory
control unit
The QuickPath Interconnect (QPI) _________ layer is used to determine the course that a packet will traverse across the available system interconnects.
link
physical
protocol
routing
Second generation computers used __________.
large-scale integration
integrated circuits
vacuum tubes
transistors
An I/O device is referred to as a __________.
register
peripheral
control device
CPU
The _________ was the world's first general-purpose electronic digital computer.
Hollerith's Counting Machine
ENIAC
MARK IV
UNIVAC
Architectural attributes include __________ .
interfaces
memory technology used
I/O mechanisms
control signals
ANo _________ is generated by a failure such as power failure or memory parity error.
timer interrupt
hardware failure interrupt
program interrupt
I/O interrupt
A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred to as a _________.
miss
disk cache
latency
virtual address
With the __________, Intel introduced the use of superscalar techniques that allow multiple instructions to execute in parallel.
Pentium
80486
8080
Core
The _________ stores data.
control unit
main memory
I/O
system bus
A _________ is a mechanism that provides for communication among CPU, main memory, and I/O.
processor
CPU interconnection
system interconnection
peripheral
The processing required for a single instruction is called aNo __________ cycle.
execute
instruction
fetch
packet
Computer _________ refers to those attributes that have a direct impact on the logical execution of a program.
specifics
organization
design
architecture
