ALU (Arithmetic Logic Unit)

CU (Control Unit)

Registers

Clock

ALU (Arithmetic Logic Unit)

CU (Control Unit)

Registers

Buses

Registers

Clock

Buses

ALU (Arithmetic Logic Unit)

Clock

Registers

CU (Control Unit)

Buses

Buses

ALU (Arithmetic Logic Unit)

Registers

Clock

Holds address of the next instruction to fetch.

Stores data temporarily during processing.

Performs arithmetic and logic operations.

Controls input and output devices.

Holds address of memory location being accessed.

Holds the data to be processed.

Holds the instruction currently being executed.

Holds the result of arithmetic operations.

Holds data or instruction fetched from memory.

Holds the address of the next instruction to be executed.

Stores the result of arithmetic operations.

Contains the opcode of the current instruction.

Holds the current instruction being decoded/executed.

Stores the result of arithmetic operations.

Manages the flow of data between memory and CPU.

Controls the timing of instruction execution.

Temporarily stores results of ALU operations.

Controls the flow of instructions in the CPU.

Stores the address of the next instruction to be executed.

Manages input and output operations.

The Program Counter (PC) holds the address of the next instruction.

The instruction is executed by the ALU.

The data is stored in memory.

The result is displayed on the monitor.

MAR (Memory Address Register)

PC (Program Counter)

IR (Instruction Register)

ACC (Accumulator)

MDR (Memory Data Register)

MAR (Memory Address Register)

IR (Instruction Register)

PC (Program Counter)

Interprets the instruction in the CIR to determine what needs to be done.

Executes the instruction directly.

Fetches the next instruction from memory.

Stores the result in the accumulator.

All the commands the CPU can understand.

The set of instructions stored in RAM.

A list of software applications installed on a computer.

The physical components of a computer system.

Number of FDE cycles per second (measured in GHz).

Amount of RAM in a computer system.

Number of cores in a processor.

Size of the hard disk drive.

Higher speed = more instructions per second.

Higher speed = less instructions per second.

Clock speed does not affect CPU performance.

Lower speed = more instructions per second.

Each core can run its own FDE cycle simultaneously.

It increases the clock speed of the CPU.

It reduces the size of the cache memory.

It decreases the power consumption of the CPU.

Stores frequently used instructions/data → faster access.

Increases the number of CPU cores.

Reduces the clock speed of the CPU.

Decreases the power consumption of the CPU.

Larger word = more data processed per cycle.

Larger word = slower clock speed.

Larger word = less memory required.

Larger word = reduced instruction set.

Wider buses = more data transferred per cycle.

Wider buses = slower CPU speed.

Bus width only affects graphics performance.

Bus width determines the number of CPU cores.

Copy address to MAR

Fetch data from memory to MDR

Program Counter (PC)

Copy to CIR

Decode & Execute via CU & ALU

Fast storage area inside CPU for temporary data

High-speed memory inside CPU for frequently accessed data

Independent processing unit within a CPU

A communication system between CPU, memory, and I/O devices

High-speed memory inside CPU for frequently accessed data

Independent processing unit within a CPU

Manages execution of instructions and timing

Performs calculations and logical operations

A. A communication system between CPU, memory, and I/O devices

B. Fast storage area inside CPU for temporary data

C. One complete FDE cycle

D. Overlapping FDE stages for faster performance

Manages execution of instructions and timing

Performs calculations and logical operations

Stores instructions

Controls data flow

Manages execution of instructions and timing

Fast storage area inside CPU for temporary data

Overlapping FDE stages for faster performance

Fetches instructions from memory

Fast storage area inside CPU for temporary data

High-speed memory inside CPU for frequently accessed data

Independent processing unit within a CPU

One complete FDE cycle

One complete FDE cycle

Overlapping FDE stages for faster performance

Manages execution of instructions and timing

Performs calculations and logical operations

Overlapping FDE stages for faster performance

Fast storage area inside CPU for temporary data

High-speed memory inside CPU for frequently accessed data

Independent processing unit within a CPU

Stores instructions

Controls data flow

Performs calculations and logic operations

Fetches instructions from memory

MAR

PC

MDR

ACC

PC

MDR

MAR

CIR

Execution

Increment PC

Decoding

Storing in MAR

To point to the next instruction in sequence, ensuring the CPU executes instructions in order.

To reset the CPU to its initial state after each instruction.

To increase the speed of the CPU by skipping instructions.

To store the result of the previous operation.

Holds the memory address of the location to be accessed (for reading or writing).

Stores the data being transferred to or from memory.

Controls the execution of instructions in the CPU.

Performs arithmetic and logic operations.

The CU directs the ALU to perform operations and manages the flow of data during the Execute stage.

The ALU stores instructions while the CU performs calculations during the Execute stage.

The CU and ALU both store data during the Execute stage.

The ALU manages memory while the CU performs arithmetic operations during the Execute stage.

A small, fast storage location within a CPU used to hold data temporarily.

A device used to connect computers to the internet.

A type of external memory used for long-term storage.

A software program that manages hardware resources.

To provide faster access to frequently used data

To increase the size of main memory

To reduce the number of CPU cores

To store permanent data

The number of instructions a CPU can execute per second

The amount of memory available in a computer

The physical size of the processor

The type of software running on the computer

Because it can execute multiple tasks simultaneously.

Because it uses less power than a single-core processor.

Because it has a higher clock speed than a single-core processor.

Because it requires less memory than a single-core processor.

Carries control signals (read/write, clock, interrupt) between CPU and other components.

Transfers data between memory and CPU.

Stores instructions for the CPU to execute.

Connects external devices to the computer system.

Data bus: transfers actual data. Address bus: carries the address of the data or instruction in memory.

Data bus: carries instructions. Address bus: transfers actual data.

Data bus: stores memory locations. Address bus: processes data.

Data bus: controls the CPU. Address bus: manages input/output devices.

ACC (Accumulator)

ALU (Arithmetic Logic Unit)

CU (Control Unit)

IR (Instruction Register)

The Control Unit interprets the binary instruction to determine which operation to perform.

The instruction is executed by the ALU.

The result is stored in memory.

The instruction is fetched from memory.

It allows overlapping stages of multiple instructions, increasing instruction throughput.

It reduces the power consumption of the CPU significantly.

It eliminates the need for cache memory in CPUs.

It increases the clock speed of the CPU without any hardware changes.

3 billion (3 × 10^9) cycles per second.

300 million (3 × 10^8) cycles per second.

30 million (3 × 10^7) cycles per second.

3 million (3 × 10^6) cycles per second.

It generally improves CPU performance by reducing memory access time.

It decreases CPU performance by increasing memory access time.

It has no effect on CPU performance.

It makes the CPU slower due to more cache misses.

Central Processing Unit

Computer Peripheral Unit

Central Power Unit

Control Processing Unit

Performs arithmetic/logic operations

Stores data temporarily

Controls input/output devices

Manages system memory

Manages instruction execution

Manages memory storage

Controls input/output devices

Handles arithmetic operations

Fast storage within CPU

Long-term data storage

Connecting external devices

Running operating system only

Memory Address Register

Main Arithmetic Register

Machine Access Register

Memory Allocation Register

Memory Data Register

Main Data Router

Machine Data Resource

Memory Device Register

Current Instruction Register

Central Input Register

Control Interface Register

Cache Index Register

Program Counter

Primary Cache

Peripheral Controller

Process Control

Accumulator

Access Control Code

Arithmetic Calculation Circuit

Address Conversion Component

Instructions per second

Amount of RAM

Number of cores

Size of cache

Data transfer pathway

Power supply unit

Cooling system

Input device

Fast temporary memory

Permanent storage device

Input device

Display screen

Processing unit in CPU

Memory storage in CPU

Cooling system in CPU

Input device for CPU

All CPU commands

The CPU's clock speed

The amount of RAM

The number of cores

Instruction fetched from memory

Data written to memory

Instruction decoded

Result stored in register

CU decodes instruction

ALU performs addition

Memory stores data

Register fetches operand

Instruction carried out, result stored in ACC

Instruction fetched from memory

Address of next instruction calculated

Data transferred to memory

PC → MAR → MDR → CIR

PC → MDR → MAR → CIR

MAR → PC → MDR → CIR

PC → CIR → MAR → MDR

Address → Decode → Control

Access → Data → Compute

Allocate → Dispatch → Complete

Analyze → Develop → Create

Use register names (PC, MAR, MDR, CIR) — they score marks!

Because registers are always visible in diagrams.

Registers are only used in programming languages.

Mentioning registers makes your answer longer.

Label registers + buses

Label only the title

Label random shapes

Label with colors only

holds, copies, transfers

writes, deletes, moves

reads, sends, receives

creates, updates, removes

PC increments so the next instruction can be fetched.

PC decrements to repeat the previous instruction.

PC remains unchanged after each instruction.

PC resets to zero after every instruction.

The MAR holds the address.

The MAR performs arithmetic operations.

The MAR stores data temporarily.

The MAR controls input/output devices.

cache/core/clock

RAM/ROM/SSD

GPU/monitor/mouse

power supply/case/fan

Describe FDE cycle

Describe RAM types

Explain GPU functions

List input devices

Hz or GHz

ms or ns

MB or GB

V or A

Fetch: Uses Program Counter (PC) and Memory Address Register (MAR) to get instruction; Decode: Uses Memory Data Register (MDR) and Current Instruction Register (CIR) to interpret instruction; Execute: Uses Accumulator (ACC) to carry out instruction.

Fetch: Uses Accumulator (ACC) to get instruction; Decode: Uses Program Counter (PC) to interpret instruction; Execute: Uses Memory Address Register (MAR) to carry out instruction.

Fetch: Uses Current Instruction Register (CIR) to get instruction; Decode: Uses Memory Address Register (MAR) to interpret instruction; Execute: Uses Program Counter (PC) to carry out instruction.

Fetch: Uses Memory Data Register (MDR) to get instruction; Decode: Uses Accumulator (ACC) to interpret instruction; Execute: Uses Memory Address Register (MAR) to carry out instruction.

ALU performs arithmetic and logic operations, CU controls instruction execution, Registers store data temporarily and all interact to process instructions.

ALU stores data, CU performs arithmetic, Registers control instruction execution.

ALU controls instruction execution, CU stores data, Registers perform arithmetic operations.

ALU, CU, and Registers only store data and do not interact during processing.

Improving processing speed and multitasking ability

Reducing power consumption and heat output

Decreasing the ability to run multiple programs

Slowing down data access and computation

A bus in a computer system is a set of wires that transfers data, addresses, and control signals between components.

A bus in a computer system is a storage device for saving files and documents.

A bus in a computer system is a software program that manages user input.

A bus in a computer system is a graphical interface for displaying images.

RAM is located farther from the CPU, is slower than cache and registers, and is used for general data storage; cache is closer and faster, used for frequently accessed data; registers are inside the CPU, fastest, used for immediate operations.

RAM is inside the CPU, fastest, used for immediate operations; cache is farther and slower, used for general data storage; registers are closer and used for frequently accessed data.

RAM, cache, and registers all have the same speed and location, but differ in size.

Cache is used for general data storage, RAM for frequently accessed data, and registers for long-term storage.

The Control Unit fetches instructions using the Program Counter, which keeps track of the next instruction to execute.

The Program Counter executes instructions while the Control Unit stores data.

The Control Unit and Program Counter both store instructions for future use.

The Program Counter controls the ALU while the Control Unit manages memory.

Von Neumann architecture uses a single memory for instructions and data, while Harvard architecture uses separate memories; examples are traditional PCs (von Neumann) and microcontrollers like AVR (Harvard).

Von Neumann architecture uses separate memories for instructions and data, while Harvard architecture uses a single memory; examples are microcontrollers like AVR (von Neumann) and traditional PCs (Harvard).

Both von Neumann and Harvard architectures use a single memory for instructions and data; examples are traditional PCs and microcontrollers like AVR.

Von Neumann architecture uses multiple CPUs, while Harvard architecture uses a single CPU; examples are supercomputers (von Neumann) and smartphones (Harvard).

The need for tasks to be independent and not require frequent communication between cores

The number of transistors in the CPU

The size of the computer's monitor

The color of the CPU casing

binary is the only language CPUs can directly process

high-level instructions are faster for CPUs to execute

binary is easier for humans to understand

high-level instructions require less memory than binary

Interrupts signal the control unit to temporarily halt current processing and address the hardware device's request before resuming.

Interrupts allow the control unit to ignore hardware device requests during processing.

The control unit automatically completes all processing before responding to any hardware device requests, regardless of interrupts.

Interrupts and the control unit do not interact when a hardware device requests attention.

MAR

PC

MDR

CIR

Data

Address

Control

Cache

Next instruction address

Data value

Current instruction

Result of calculation

Data is stored in MAR

PC increments by one

ALU performs operation

Cache is cleared

Larger hard disk

More cores

Smaller cache

Slower clock

It is magnetic

It is located inside the CPU

It is secondary storage

It uses slower buses

ACC

MAR

PC

CU

Clock speed

Cache size

Number of cores

Monitor resolution

Execute → Decode → Fetch

Fetch → Execute → Decode

Decode → Fetch → Execute

Fetch → Decode → Execute

Fetch: Uses the Program Counter (PC) and Memory Address Register (MAR) to get the instruction; Decode: Uses the Memory Data Register (MDR) and Current Instruction Register (CIR) to interpret the instruction; Execute: Uses the Accumulator (ACC) to carry out the instruction.

Fetch: Uses the Accumulator (ACC) to get the instruction; Decode: Uses the Program Counter (PC) to interpret the instruction; Execute: Uses the Memory Address Register (MAR) to carry out the instruction.

Fetch: Uses the Memory Data Register (MDR) to get the instruction; Decode: Uses the Accumulator (ACC) to interpret the instruction; Execute: Uses the Program Counter (PC) to carry out the instruction.

Fetch: Uses the Current Instruction Register (CIR) to get the instruction; Decode: Uses the Memory Address Register (MAR) to interpret the instruction; Execute: Uses the Memory Data Register (MDR) to carry out the instruction.

Fetch → Decode → Execute; PC holds address, MAR stores address, MDR holds data, CIR stores instruction, ACC processes data; CU controls flow via buses and signals.

Execute → Decode → Fetch; ACC stores address, MAR holds data, MDR processes instruction, CIR controls flow, PC manages signals.

Decode → Fetch → Execute; MAR holds instruction, MDR stores address, ACC manages control, CIR processes data, PC controls buses.

Fetch → Execute → Decode; MDR stores address, ACC holds instruction, MAR processes data, CIR manages signals, PC controls flow.

Clock speed, cache size, and number of cores

Screen resolution, battery size, and color depth

Hard disk capacity, USB ports, and keyboard type

Operating system version, monitor size, and mouse sensitivity

The CU directs operations, the ALU performs calculations, and Registers store data temporarily.

The CU stores data, the ALU directs operations, and Registers perform calculations.

The CU performs calculations, the ALU stores data, and Registers direct operations.

The CU and ALU both store data, while Registers perform all operations.