WorksheetsDFA ONLINE QUIZ EXAM
Total questions: 60
Worksheet time: 30mins
Name
Class
Date
1.
Which number system uses base 10?
a)
Binary
b)
Octal
c)
Decimal
d)
Hexadecimal
2.
The largest single digit in the Hexadecimal system is represented by:
a)
9.0
b)
A
c)
F
d)
10.0
3.
Which code is used for error detection and uses only one bit change between successive numbers?
a)
BCD
b)
Excess-3
c)
Gray Code
d)
ASCII
4.
Which circuit performs the addition of two single binary bits?
a)
Full Adder
b)
Half Adder
c)
Parallel Adder
d)
Serial Adder
5.
A logic gate that acts as a universal gate is the:
a)
OR
b)
AND
c)
XOR
d)
NAND
6.
Which circuit is used for subtracting two single binary bits?
a)
Full Adder
b)
Half Subtractor
c)
Parallel Adder
d)
BCD Adder
7.
Which logic gate outputs HIGH only when its inputs are different?
a)
AND
b)
OR
c)
NOT
d)
XOR
8.
What is the primary purpose of using Complements in digital systems?
a)
Data encryption
b)
Binary subtraction
c)
Logic simplification
d)
Code conversion
9.
The BCD (Binary Coded Decimal) code represents each decimal digit with how many bits?
a)
2.0
b)
4.0
c)
8.0
d)
16.0
10.
What is the simplest form of logic expression minimization?
a)
Full Adder
b)
Karnaugh Map
c)
Strobe Control
d)
DMA
11.
In a Boolean expression, a term that contains all variables, either complemented or uncomplemented, is a:
a)
Implicant
b)
Canonical Form
c)
Don't Care
d)
Minterm/Maxterm
12.
Which type of logic circuit's output depends only on its current inputs?
a)
Sequential
b)
Multiplexer
c)
Combinational
d)
Flip-Flop
13.
A circuit whose output depends on both current inputs and previous outputs is:
a)
Combinational
b)
Sequential
c)
Decoder
d)
Encoder
14.
Which device is a basic one-bit memory element?
a)
Decoder
b)
Encoder
c)
Multiplexer
d)
Flip-Flop
15.
Which flip-flop is known for having a "race around" condition if both inputs are HIGH?
a)
RS Flip-Flop
b)
D Flip-Flop
c)
T Flip-Flop
d)
JK Flip-Flop
16.
A device that selects one of many input lines and routes it to a single output line is a:
a)
Demultiplexer
b)
Decoder
c)
Encoder
d)
Multiplexer
17.
A device that takes a single input and distributes it to one of many output lines is a:
a)
Multiplexer
b)
Encoder
c)
Demultiplexer
d)
Flip-Flop
18.
A circuit that converts binary code into a unique output line (e.g., 2-to-4) is a:
a)
Multiplexer
b)
Decoder
c)
Encoder
d)
Shift Register
19.
A sequential circuit used to store and move binary data is a:
a)
Counter
b)
Multiplexer
c)
Shift Register
d)
Full Adder
20.
A device that counts the number of clock pulses is called a:
a)
Multiplexer
b)
Shift Register
c)
Decoder
d)
Counter
21.
The interface that allows the CPU to talk to peripheral devices is the:
a)
Main Memory
b)
I/O Interface
c)
Cache Memory
d)
Hard Drive
22.
A separate address space for I/O devices distinct from memory is known as:
a)
Memory-Mapped I/O
b)
Isolated I/O
c)
DMA Transfer
d)
Asynchronous Transfer
23.
Using the same address space for both memory and I/O devices is called:
a)
Isolated I/O
b)
Memory-Mapped I/O
c)
Strobe Control
d)
Priority Interrupt
24.
The data transfer method using a single control signal from the source to the destination is:
a)
Handshaking
b)
Strobe Control
c)
DMA Transfer
d)
Daisy-Chaining
25.
The data transfer method using two-way signaling between the source and destination is:
a)
Strobe Control
b)
Handshaking
c)
Priority Interrupt
d)
Serial Communication
26.
Which mode of transfer bypasses the CPU for data movement between I/O and memory?
a)
Interrupt-driven
b)
Programmed I/O
c)
Direct Memory Access (DMA)
d)
Serial Communication
27.
A method for handling multiple interrupt requests by connecting devices in series is:
a)
Parallel Priority
b)
Handshaking
c)
Daisy-Chaining Priority
d)
DMA Controller
28.
The dedicated hardware component that manages DMA transfers is the:
a)
CPU
b)
Input-Output Processor
c)
DMA Controller
d)
Cache Memory
29.
Which protocol sends data one bit at a time over a single channel?
a)
DMA Transfer
b)
Parallel Binary Adder
c)
Serial Communication
d)
Strobe Control
30.
The technique used to send all characters, including control characters, in serial communication is called:
a)
Character Oriented Protocol
b)
Data Transparency
c)
Priority Interrupt
d)
Bit Oriented Protocol
31.
What is the top level in the Memory Hierarchy?
a)
Main Memory
b)
Cache Memory
c)
Hard Disk
d)
Registers
32.
The largest capacity and slowest memory in the hierarchy is generally the:
a)
Cache Memory
b)
Main Memory
c)
Auxiliary/Mass Storage
d)
Associative Memory
33.
Which type of memory is addressed by its content rather than by a specific address?
a)
Main Memory
b)
Cache Memory
c)
Associative Memory
d)
Read-Only Memory
34.
Which type of memory is located closest to the CPU core?
a)
Main Memory
b)
Cache Memory
c)
Hard Drive
d)
Auxiliary Memory
35.
A common technique where blocks of main memory can map to any cache line is:
a)
Direct Mapping
b)
Set-Associative Mapping
c)
Associative Mapping
d)
DMA Mapping
36.
Which cache mapping technique is the simplest but suffers from the highest conflict rate?
a)
Associative Mapping
b)
Set-Associative Mapping
c)
Direct Mapping
d)
Interconnection Structure
37.
Which cache mapping technique is a compromise between the other two?
a)
Associative Mapping
b)
Set-Associative Mapping
c)
Direct Mapping
d)
DMA Transfer
38.
In a multiprocessor system, the method used to ensure only one CPU accesses a shared resource is:
a)
Interconnection Structure
b)
Inter Processor Arbitration
c)
Cache Initialization
d)
Serial Communication
39.
When the CPU sends status and control commands to the I/O Processor, this is called:
a)
DMA Transfer
b)
Inter Processor Arbitration
c)
CPU-IOP Communication
d)
Memory Bus Transfer
40.
What is the primary function of the Match Logic in Associative Memory?
a)
Calculate address
b)
Write data
c)
Compare input content
d)
Initialize cache
41.
Which arithmetic circuit requires three inputs (two data bits and one carry-in)?
a)
Half Adder
b)
Full Adder
c)
Half Subtractor
d)
Parallel Subtractor
42.
The number of bits in a single precision Floating Point Representation is typically:
a)
8.0
b)
16.0
c)
32.0
d)
64.0
43.
Which form of Boolean expression is a product of maxterms?
a)
Sum of Products (SOP)
b)
Product of Sums (POS)
c)
Canonical Form 1
d)
Implicant
44.
Which logic gate is derived from combining an OR gate and a NOT gate?
a)
NAND
b)
XOR
c)
NOR
d)
AND
45.
What is the primary purpose of a Parallel Binary Adder?
a)
Add one bit
b)
Add data sequentially
c)
Add multiple bits simultaneously
d)
Convert code
46.
What is the key characteristic of Asynchronous Data Transfer?
a)
Fixed timing
b)
Dependent on a clock
c)
No common clock/flexible timing
d)
Only uses DMA
47.
Which sequential circuit loads data from the input when the clock is active, and the enable signal is asserted?
a)
Counter
b)
Multiplexer
c)
Register
d)
Decoder
48.
What does the T in T Flip-Flop stand for?
a)
Time
b)
True
c)
Toggle
d)
Transfer
49.
In a Parallel Binary Subtractor, subtraction is typically done using:
a)
Logic simplification
b)
1's Complement
c)
2's Complement
d)
Gray Code
50.
Which addressing scheme is used by Associative Memory for its unique feature?
a)
Address-based
b)
Content-based
c)
Index-based
d)
Direct-mapped
51.
In Bit Oriented Protocol for serial communication, control information is distinguished by:
a)
Special characters
b)
Data transparency
c)
Flag sequences
d)
Handshaking
52.
The process of filling the cache with initial data blocks is called:
a)
Arbitration
b)
Mapping
c)
Initialization
d)
Match Logic
53.
Which component ensures mutual exclusion in a Multiprocessor system?
a)
DMA Controller
b)
Interconnection Structure
c)
Arbitration Logic
d)
Memory Bus
54.
What is the benefit of the Excess-3 Code?
a)
Error detection
b)
Self-complementing
c)
Simplifies addition
d)
Floating point
55.
In the Karnaugh Map, a group of adjacent 1s that covers the most terms is called a/an:
a)
SOP
b)
POS
c)
Implicant
d)
Maxterm
56.
What does the S in RS Flip-Flop stand for?
a)
Select
b)
Start
c)
Set
d)
Stop
57.
Which type of transfer prioritizes I/O devices over CPU access to the bus?
a)
DMA Transfer
b)
Memory-Mapped I/O
c)
Strobe Control
d)
Character Oriented Protocol
58.
What is the benefit of using NOR and NAND gates as universal gates?
a)
Faster speed
b)
Low power
c)
Low cost/Fewer chips
d)
Simplified logic
59.
The logic that determines which of several devices gets control of a shared bus is called:
a)
Priority Interrupt
b)
Arbitration
c)
Strobe Control
d)
Handshaking
60.
What is the primary role of the I/O Bus compared to the Memory Bus?
a)
Higher speed
b)
Simpler protocol
c)
Connects peripherals/slower speed
d)
Connects CPU to Cache
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