WorksheetsUnit 1: Digital Signals and Number Systems
Total questions: 96
Worksheet time: 48mins
Which statement best characterizes an analog signal?
It has discrete values
It represents information only using binary digits
It varies continuously over time
It is used exclusively in computers
Why are digital signals preferred over analog signals in computer systems?
They are continuous
They are immune to noise
They are slower to process
They use infinite voltage levels
Find the binary equivalent of the decimal number 13.
1011
1101
1001
1110
Which of the following is a valid octal number (base-8)?
178
88
725
91
The hexadecimal number 1A is equivalent to which decimal value?
26
27
18
16
Compute 1011 + 1101 in binary.
10111
11000
11100
10000
Compute 1101 − 101 in binary.
1000
1010
1110
1001
Which logic gate outputs HIGH only when all inputs are HIGH?
OR
NAND
AND
XOR
What is the output of a NOT gate?
Always 1
The same as the input
The complement of the input
0 if input is 0
According to Boolean algebra, A + A equals:
0
A
1
A'
A don’t care condition (X) in Boolean simplification can be treated as:
Always 0
Always 1
Either 0 or 1, whichever simplifies
Eliminated from the circuit
A completely specified Boolean function means:
Don’t care conditions are present
All input combinations have defined output
Some outputs are unknown
No inputs are present
Incompletely specified Boolean functions are represented using:
Only minterms
Don’t care conditions
Binary only
SOP form only
Determine the binary equivalent of octal number 17.
1111
11001
10001
1000
Which gate gives a LOW output only when all inputs are HIGH?
NAND
NOR
XOR
XNOR
Don’t care conditions in Boolean expressions are primarily used for:
Increasing circuit cost
Optimising the logic function
Removing minterms entirely
Adding extra inputs
A logic circuit with inputs A, B, C goes to a NAND gate, followed by a NOT gate. Its overall output is equivalent to:
A + B + C
ABC
A ⊕ B ⊕ C
A' + B' + C'
Find the hexadecimal equivalent of the binary number 11110110.1101.
F6.D
E7.6
D7.1
F6.C
What is the number of minterms in a 4‑variable Boolean function?
4
8
16
32
Simplify the expression using Boolean algebra: AB + A'B + AB'
A + B
B' + A'
A ⊕ B
A + B'
What is the simplified form of the Boolean expression: A + AB?
B
A
AB
A + B
Which of the following is a valid group in a K‑map?
3 adjacent 1s
Diagonal grouping
2, 4, or 8 adjacent 1s
Random 1s
From a 3‑variable K‑map for A, B, C with minterms 1, 3, 5, and 7, what is the simplified expression?
A'B'
B
C
B + C
The Quine‑McCluskey method is also known as which of the following?
Algebraic method
Tabular method
Karnaugh method
DeMorgan method
The function F = A' + B can be implemented using which gate family?
NOT and OR gates
AND and NOT gates
NOR only
NAND only
What is the complement of the Boolean expression A + B?
A' + B'
AB
A'B'
A + B'
Which of the following is not a valid group in a 4‑variable K‑map?
1 cell
2 cells
5 cells
8 cells
In Quine‑McCluskey, a table entry with two '-'s represents what?
One minterm
Two minterms
Four minterms
Don’t care term
Universal gates can be used to build which of the following?
Any logic circuit
Only SOP forms
Only combinational logic
Only arithmetic circuits
Which statement is true regarding the function F = AB + A'B + A'B'?
F is always equal to 1
F = A + B
F simplifies to A + B
F simplifies to A ⊕ B
The circuit implementing F = A'B + AB' is called which logic function?
XNOR
NOR
XOR
NAND
In the Quine‑McCluskey method, what is the significance of a term that covers both minterm 5 (0101) and minterm 7 (0111)?
Difference in 2 bits
Invalid pairing
Valid pairing with one variable eliminated
Group with don’t care
A group of eight 1s in a 4‑variable K‑map represents which simplification?
A single literal
A product term with two literals
A don’t care
A constant 1
A function F(A,B,C) has minterms 0, 1, 2, 5, and don’t‑care terms 3, 7. What is the minimized expression using a K‑map?
A'C' + B
A' + B
A'C + B'C'
A' + C
In the Quine‑McCluskey method, the initial grouping is based on which criterion?
Output values
Number of variables
Number of 1’s in the binary representation of minterms
Prime implicants
Combinational circuits are defined as those whose output depends on which of the following?
Both present and past inputs
Only current inputs
Only clock pulses
Feedback
Identify the basic building blocks of combinational logic.
Flip-flops
Latches
Logic gates
Registers
How many inputs and outputs does a half adder have?
2 inputs, 1 output
2 inputs, 2 outputs
1 input, 2 outputs
3 inputs, 1 output
Select the correct output expressions for a half adder with inputs A and B.
Sum = A XOR B; Carry = A AND B
Sum = A OR B; Carry = A AND B
Sum = A XOR B; Carry = A OR B
Sum = A AND B; Carry = A OR B
Which gate-level expression describes the carry-out of a full adder with inputs A, B, and Cin?
AB + BC + AC
A ⊕ B
A ⊕ B ⊕ Cin
A + B + C
A 4-bit parallel adder adds:
4 bits to a 1-bit number
4 bits + 4 bits
2 bits at a time
1 bit per clock
What does a half subtractor produce for inputs A and B?
Difference and Sum
Difference and Borrow
Carry and Sum
Borrow and Carry
In a half subtractor, the borrow output is given by which expression?
A'B
AB'
A XOR B
A AND B
Which of the following is not an output of a digital comparator?
A = B
A > B
A < B
A XOR B
A 4-bit comparator compares which of the following?
One 4-bit input with 1-bit
Two 4-bit binary numbers
Four 1-bit numbers
Two decimal numbers
A 3-to-8 line decoder has:
3 inputs and 8 outputs
8 inputs and 3 outputs
3 inputs and 3 outputs
8 inputs and 1 output
An 8-to-3 encoder has:
8 inputs, 3 outputs
3 inputs, 8 outputs
3 inputs, 3 outputs
2 outputs, 4 inputs
Which statement correctly defines a multiplexer?
Selects one input from many inputs
Sends multiple outputs to one input
Adds two binary numbers
Compares two numbers
How many select lines does a 4-to-1 multiplexer require?
1
2
3
4
The number of input lines in an 8:1 multiplexer is:
8
3
4
2
A multiplexer functions as a:
Data distributor
Data selector
Decoder
Comparator
Evaluate the Boolean function F = A·(B + C). What is F when A = 1, B = 0, and C = 1?
0
1
Undefined
Cannot be determined
Which rule is true about group formation in Karnaugh maps (K-maps)?
Groups must include diagonal cells
Groups can include only 2 minterms
Groups must be powers of 2
Groups can overlap only once
Given a 1-bit full adder, which input combination will produce a carry-out when Cin = 0?
A = 0, B = 0
A = 1, B = 0
A = 0, B = 1
A = 1, B = 1
For a half subtractor with inputs A and B, which condition yields Borrow = 1?
A = 1, B = 1
A = 1, B = 0
A = 0, B = 1
A = 0, B = 0
Which device translates a binary input to a one-hot output pattern?
Encoder
Decoder
Comparator
Multiplexer
Which device converts a one-hot input pattern into its binary code?
Multiplexer
Decoder
Encoder
Comparator
A 2-input XOR gate is used in a half adder for which output?
Carry only
Sum only
Both Sum and Carry
Neither Sum nor Carry
In designing a selection network, which component would you use to route one of several data inputs to a single output based on select lines?
Decoder
Multiplexer
Comparator
Half adder
Which statement correctly contrasts encoders and decoders?
Encoders increase the number of outputs; decoders reduce them
Encoders map one-hot inputs to binary; decoders map binary inputs to one-hot outputs
Encoders perform comparisons; decoders perform selection
Encoders require select lines; decoders do not
A bistable circuit can be used as which of the following? Choose the best option based on digital logic fundamentals.
Decoder
Counter
Memory element
Comparator
What is the main difference between a latch and a flip-flop in terms of their operation?
Clock dependency
Output type
Number of inputs
Number of states
In an SR latch made from NOR gates, if S = 1 and R = 0, what is the output state? Assume standard active-high inputs.
Q = 1, Q’ = 0
Q = 0, Q’ = 1
Q = Q’ = 1
Q = Q’ = 0
Which expression represents the characteristic equation of the SR flip-flop?
Q’= R + S
Q’= Q
Q’= S + R’Q
Q’= S + R’
What is the primary purpose of a master–slave configuration in flip-flops?
Reduce cost
Prevent the race-around condition
Increase speed
Increase invalid states
Which equation correctly describes the next state of a T flip-flop? Use standard notation where ⊕ denotes XOR.
Q’= Q
Q’= D
Q’= T ⊕ Q
Q’= T + Q
If T = 1 in a T flip-flop, what is the next output state relative to the current state?
Set
Reset
No change
Toggle
The expression Q’= Q indicates which behavior of a flip-flop?
The flip-flop toggles
The output remains unchanged
The flip-flop resets
The flip-flop sets
In a JK flip-flop, if J and K inputs remain HIGH for a long duration, what will happen?
Flip-flop will latch
Flip-flop will toggle continuously
Outputs freeze
Nothing
From the characteristic equation of a JK flip-flop, deduce Q’ if Q = 1, J = 1, K = 0.
1
0
Toggle
Invalid
The JK flip-flop behaves like a T flip-flop when which condition on J and K holds?
J = 1, K = 0
J = K = 1
J = 0, K = 1
J = K = 0
To convert an SR flip-flop to a D flip-flop using input connections, which mapping is correct?
S = D, R = D’
S = D, R = 0
S = D’, R = D
S= 1, R= 1
What is the characteristic equation of a D flip-flop?
Q’= D
Q’= T ⊕ Q
Q’= JQ’ + K’Q
Q’= S + R’
A bistable element is a circuit that has which property?
One stable state
Two stable states
No stable state
Multiple outputs
A D flip-flop eliminates the invalid state encountered in which device?
SR flip-flop
JK flip-flop
T flip-flop
Master–slave
In a master–slave JK flip-flop, the slave is enabled under which clock condition?
The clock is HIGH
The clock is LOW
The clock is rising
The clock is falling
Which device among latches and flip-flops is directly used to prevent the race-around condition without changing the logic family?
Asynchronous latch
Master–slave flip-flop
Edge-triggered inverter
Transparent buffer
Identify the correct statement about characteristic equations: they relate the next state Q’ to present inputs and present state. Which equation fits the JK flip-flop under standard form?
Q’= JQ’ + K’Q
Q’= JQ + K’Q’
Q’= JQ’ + KQ’
Q’= J’Q + KQ
Which latch/flip-flop type has precisely one data input and directly transfers it to the next state on the clock edge?
SR latch
JK flip-flop
D flip-flop
T flip-flop
A 4-bit shift register implemented with D flip-flops can store how many bits of data at a time?
2 bits
8 bits
4 bits
16 bits
In a right shift register using D flip-flops, data moves in which direction between stages?
From right to left
From left to right
Bi-directionally
Randomly
A synchronous MOD-16 counter requires how many flip-flops?
4
3
5
6
A MOD-5 synchronous counter cycles through how many distinct states?
4
10
6
5
In synchronous counter design, Karnaugh maps are primarily used to:
Store logic
Identify hazards
Simplify D/T input logic
Generate toggles
A synchronous counter designed with D flip-flops counts 000 → 001 → 010 → 011. What is its modulus?
MOD-3
MOD-4
MOD-2
Ring counter
For a MOD-6 counter implemented using T flip-flops, how many T flip-flops are needed?
2
3
4
6
Which statement correctly characterizes synchronous counters?
Trigger on random edges
Have no timing control
All flip-flops are triggered at the same time
Require fewer gates than ripple
In a synchronous 4-bit up-counter using T flip-flops, what should the T inputs be?
All 1
T0 = 1, T1 = Q0, T2 = Q0·Q1, T3 = Q0·Q1·Q2
T = Q
Tied to ground
In a synchronous counter, all flip-flops are triggered by:
Their Q output
Feedback logic
A ring oscillator
The same clock signal
A 3-bit ripple down-counter using T flip-flops starts at 111. What is the next state after a clock pulse?
000
110
001
011
In a ripple counter, each flip-flop is triggered by:
A global clock
Its own clock
The output of the previous flip-flop
Tied to logic 1
In an asynchronous 3-bit up-counter using T flip-flops, how many states are possible?
4
6
8
16
Which type of shift register can perform both left and right shifts?
SISO
PIPO
SIPO
Bidirectional
A parallel-in, parallel-out (PIPO) shift register most closely behaves like a:
Memory
Counter
Encoder
Demux
In a D flip-flop based shift register, the output of each stage is connected to which input of the next stage?
The clock input of the next
The D input of the next
The Q' of the previous
Ground
Which flip-flop type is best suited for constructing shift registers?
T
D
SR
JK
