WorksheetsCascade 2025- Analog Design Quiz
Total questions: 35
Worksheet time: 43mins
The output of a 3-input XOR gate is 1 only when:
All inputs are 1
Even number of inputs are 1
Odd number of inputs are 1
All inputs are 0
What will be the output Y of the following Verilog code?
module logic_gate(input A, B, C, output Y);
assign Y = ~(A & B) | C;
endmodule
If A = 1, B = 1, and C = 0, then the output Y is:
0
1
Error
None of the above
In a 4-variable K-map, how many prime implicants can exist maximum?
4
8
10
16
A full adder can be implemented using:
Two half adders and one OR gate
Two XOR gates only
One half adder and one AND gate
Three NAND gates
A JK flip-flop behaves as a T flip-flop when:
J=0, K=0
J=1, K=0
J=0, K=1
J=1, K=1
The minimal expression for F = A’BC + AB’C + ABC’ is:
AB + BC + AC
A ⊕ B ⊕ C
(A + B)(B + C)(C + A)
A’B’C’
A 4:1 multiplexer can implement how many distinct Boolean functions of 2 variables?
4
8
16
64
Which flip-flop is edge-triggered by default in IC 7474?
T
SR
JK
D
The main advantage of synchronous counters over asynchronous is:
Lower cost
Higher speed
Simple design
No clock needed
In a 2-input XOR gate, if both inputs are complemented, output will:
Invert
Remain same
Become 0
Become 1
Which of the following logic families has the lowest power consumption?
TTL
ECL
CMOS
RTL
A 4-bit binary counter counts from 0000 to 1111. What will be the count after 25 clock pulses?
0001
1000
1001
1010
______ architecture is used to design VLS
Single open circuit
Single open circuit
System on a chip
System on a circuit
. _________ is used in logic design of VLSI.
FIFO
FILO
LILO
LILO
Adder using _________ technology can be used for speed improvement.
BiCMOS
CMOS
nMOS
pmos
Which of the following Verilog statements correctly describes a 2-input AND gate?
assign Y = A & B;
Y = A && B;
Y <= A & B;
Y <= A & B;
For the Boolean function F(A,B,C,D) = Σ(0,2,5,7,8,10,13,15), the minimal SOP expression after K-map simplification will contain how many terms?
2
3
4
5
Which of the following Verilog statements can cause a race condition if used incorrectly inside a clocked always block?
assign Y = A & B;
Y = A & B;
Y <= A & B;
always @ (A or B) Y = A & B;
A VLSI chip designed using BiCMOS technology primarily aims to:
Reduce propagation delay and power consumption simultaneously
Combine the speed of bipolar with low power of CMOS
Replace MOSFETs with BJTs
Increase chip density by using only MOS devices
A 3-bit synchronous counter using T flip-flops has the T inputs as T1=Q0Q2’, T2=Q1’, and T3=1
The count sequence will be:
0-1-3-7-6-4-5-2
0-1-3-2-6-7-5-4
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
In a 4-bit DAC with output range 0–15 V, what analog output corresponds to the binary input 1010?
9 V
10 V
7.5 V
15 V
Find Y, If A=B=1 and C=0
1
0
Error
None of the above
module test2(input A, B, C, output reg Y);
always @(A or B or C)
if (A & B)
Y = C;
else
Y = ~C;
Endmodule
If A=1, B=1, C=0 → What is the output?
0
1
Error
Undefined
A 2’s complement 8-bit adder adds 11101010 and 00010111. The result (ignoring overflow) is:
11110001
00000001
11111111
11100001
module test2;
reg a, b, c;
initial begin
a = 0; b = 1; c = 0;
a <= b;
b <= c;
$display("%b %b %b", a, b, c);
end
endmodule
Output?
0 0 0
1 0 0
0 1 0
1 1 0
In Verilog, a blocking assignment (=) executes __________, while a non-blocking assignment (<=) executes __________.
Sequentially, concurrently
Concurrently, sequentially
Randomly, deterministically
In parallel, in series
In Verilog bubble sort implementation, the outer loop controls __________, while the inner loop performs __________.
Comparisons, swapping
Swapping, initialization
Passes, comparisons
Sorting, memory allocation
In a full adder, the carry-out equation is given by:
Cout = A⊕B⊕Cin
Cout = AB + BCin + ACin
Cout = (A⊕B)Cin
Cout = (A+B+Cin)’
genvar i;
generate
for (i=0; i<4; i=i+1)
assign sum[i] = A[i] ^ B[i];
endgenerate
This code implements:
4-bit adder
4-bit XOR gate array
4-bit comparator
4-bit subtractor
always @(posedge clk)
case(state)
2'b00: state <= 2'b01;
2'b01: state <= 2'b10;
2'b10: state <= 2'b10;
endcase
This FSM:
Counts 0→1→2→3 cyclically
Has a trap state at 2
Is asynchronous
Is Mealy type
if (A > B) begin
temp = A;
A = B;
B = temp;
end
To synthesize correctly in hardware, this must be placed inside:
initial block
always_comb block
always @(posedge clk
assign statements
module test;
reg [3:0] a = 4'b1010;
reg [3:0] b = 4'b1100;
initial begin
a = a & b;
$display("%b", a);
end
endmodule
Output:
1110
1000
1010
1100
. The main performance improvement in a pipelined adder compared to ripple-carry adder is due to:
Reduction in carry propagation time
Parallelism through register insertion
Faster full-adder logic
Reduced gate count
Which FSM encoding scheme minimizes power consumption by ensuring only one bit changes between consecutive states?
Binary encoding
One-hot encoding
Gray encoding
Johnson encoding
In microprocessor 8086 convert the location of register (3A7)h to decimal
897
923
935
947
