WorksheetsVon Neumann Architecture
Total questions: 32
Worksheet time: 16mins
Which statement best describes the stored-program concept underlying the Von Neumann architecture?
Program instructions and data are stored in separate dedicated memories to prevent interference
Instructions and data share the same memory, allowing the CPU to fetch both from a single addressable space
Programs are hard-wired into the CPU and cannot be modified during execution
Data is streamed directly from input devices to the ALU without being stored
In the Von Neumann architecture, which component is primarily responsible for executing arithmetic and logical operations such as ADD, SUBTRACT, AND, OR, and NOT?
Control Unit (CU)
Arithmetic and Logic Unit (ALU)
Memory Unit
Program Counter (PC)
Which role is performed by the Control Unit (CU) in the CPU?
Storing intermediate arithmetic results
Performing mathematical calculations
Managing timing and sending control signals to coordinate the ALU, memory, and I/O devices
Holding the current instruction during processing
Which statement about the Memory Unit in the Von Neumann architecture is correct?
It consists of cache only and is slower than secondary storage
It consists of RAM partitions, each with an address and contents, and is directly accessible by the CPU
It only stores program instructions, not data
It is a permanent memory used to archive programs
Which register contains the memory location (address) of data that needs to be accessed?
MDR (Memory Data Register)
ACC (Accumulator)
PC (Program Counter)
MAR (Memory Address Register)
What does the MDR (Memory Data Register) hold?
The next instruction’s address
Data being transferred to or from memory
Intermediate arithmetic results
The current instruction during processing
Which register stores intermediate arithmetic and logic results?
PC
ACC
CIR
MAR
Which register contains the address of the next instruction to be executed?
CIR
ACC
PC
MDR
Which register contains the current instruction during processing?
MAR
CIR
ACC
PC
Which bus carries addresses (but not data) between the processor and memory?
Data Bus
Control Bus
Address Bus
Instruction Bus
Which bus carries control signals and commands to coordinate activities within the computer?
Address Bus
Data Bus
Control Bus
Execution Bus
Which bus carries data between the processor, memory, and input/output devices?
Instruction Bus
Data Bus
Control Bus
Address Bus
Select all components that are part of the CPU in the Von Neumann architecture.
Control Unit (CU)
Arithmetic and Logic Unit (ALU)
Memory Unit (RAM)
Registers
In the fetch-decode-execute cycle, which pair of registers most directly holds the address to fetch and the instruction being processed?
MAR and CIR
ACC and MDR
PC and ACC
MDR and PC
Which component provides timing and control signals required by other computer components?
ALU
CU
Memory Unit
Address Bus
Which description best matches the diagram of the CPU showing CU, ALU, registers (PC, CIR, ACC, MAR, MDR), and arrows to input/output devices?
A depiction of secondary storage connections
A schematic of the Central Processing Unit with Control Unit, Arithmetic/Logic Unit, and registers interfacing with input/output and memory
A network diagram illustrating multiple processors
An illustration of only the memory hierarchy
What is the primary purpose of loading data from permanent storage into RAM in this architecture?
To ensure data is archived securely
To allow the CPU to operate much quicker by accessing fast, directly accessible memory
To compress data before processing
To bypass the control unit for faster execution
Which combination correctly pairs a bus with its function?
Address Bus — carries control signals; Control Bus — carries memory addresses
Data Bus — carries addresses; Address Bus — carries control signals
Control Bus — carries control commands; Data Bus — carries data
Address Bus — carries data; Data Bus — carries instructions only
Which statement about the CPU is accurate according to the Von Neumann architecture summary?
The CPU is an input/output device used to store programs
The CPU contains the ALU, CU, and a variety of registers responsible for executing program instructions
The CPU is synonymous with RAM and secondary storage
The CPU performs only control operations and no arithmetic
Which registers are explicitly listed in the diagram and table for the Von Neumann architecture? Select all that apply.
MAR, MDR, ACC, PC, CIR
IR, SR, DR, BR
AX, BX, CX, DX
TLB, MMU, FPU
In the Fetch Decode Execute Cycle, what does the Program Counter (PC) hold at the start of a fetch?
The binary code of the next instruction
The address of the next instruction in memory
The current instruction being executed
The decoded control signals for execution
Which register receives the address from the Program Counter via the address bus during the fetch stage?
Memory Data Register (MDR)
Current Instruction Register (CIR)
Memory Address Register (MAR)
Accumulator
According to the cycle description, which operation follows copying the PC to the MAR?
Increment the PC
Copy MDR into the CIR
Lookup the MAR’s address and load contents into the MDR
Decode and execute the instruction
Select the correct sequence of the first three steps of the Fetch Decode Execute Cycle.
PC holds address → PC copied to MAR → MAR looked up and contents loaded to MDR
PC holds address → MAR looked up → PC copied to MDR
PC copied to MAR → PC incremented → MDR copied to CIR
PC holds address → MDR copied to CIR → PC incremented
What is placed into the Current Instruction Register (CIR) during the cycle?
The decoded control signals
The address of the next instruction
The contents of the Memory Data Register (MDR)
The value of the Program Counter (PC)
When is the Program Counter incremented in the described cycle?
Immediately after decoding the instruction
Right after the PC is copied to the MAR
After copying MDR contents into the CIR
Before fetching the contents into the MDR
Which registers are directly involved in transferring the instruction from memory to the CPU for decoding?
MAR
MDR
CIR
ALU
During execution, what mechanism is described as sending signals to various computer components?
Data bus originating from the MDR
Control bus issuing signals after decoding
Address bus driven by the PC
Arithmetic Logic Unit dispatching addresses
Match each register to its role in the Fetch Decode Execute Cycle.
PC: holds address of next instruction
MAR: receives address from PC
MDR: stores instruction fetched from memory
CIR: holds current instruction ready for decoding
Which statement best differentiates MAR from MDR in the cycle?
MAR stores the fetched instruction; MDR stores the address to be accessed
MAR holds an address to be looked up; MDR holds the contents retrieved from that address
Both MAR and MDR hold decoded control signals
MAR increments automatically while MDR remains constant
Identify the step that directly precedes instruction decoding in the outlined cycle.
PC is incremented by 1
PC is copied to MAR
MAR is looked up and contents copied to MDR
Execution signals are sent on the control bus
According to the summarized list, what is the final action of the cycle before repeating?
Copy PC to MAR again
Store results in the MDR
Decode the instruction and then execute by issuing control signals
Reset the Program Counter to zero
