WorksheetsCPE 411 Final Exam(Computer Architecture & Organization)
Total questions: 66
Worksheet time: 2hrs 16mins
Which memory level is the fastest, smallest, and most expensive per bit in the memory hierarchy?
Cache
Main Memory (RAM)
Secondary Storage
Registers
The principle that if an item is referenced, items with nearby addresses will also tend to be referenced soon is known as:
Temporal Locality
Spatial Locality
Cache Hit
Demand Paging
In cache mapping, the technique where each block of main memory maps to exactly one location in the cache is:
Fully Associative
Set-Associative
Direct-Mapped
Random Replacement
Which type of RAM needs to be periodically "refreshed" to retain its data?
DRAM (Dynamic RAM)
SRAM (Static RAM)
Registers
Cache Memory
The core idea of Paging is to break a program's virtual address space into equal-sized pages and physical memory into equal-sized:
Registers
Blocks
Sets
Frames
SRAM is primarily used for which component in a computer system?
Main Memory (RAM)
Cache memory (L1, L2, L3)
Hard Disk Drives
Virtual Memory
Which measurement is described as a latency measure (how long until the first bit arrives)?
Bandwidth
Throughput
Access Time
Hit Rate
The primary goal of I/O Interfacing is to:
Increase the speed of the CPU.
Bypass the use of memory.
Efficiently manage the flow of data between components with vastly different speeds.
Perform all I/O operations using only the CPU.
The I/O addressing scheme where device registers are addressed like standard memory locations using common instructions (LOAD/STORE) is:
Isolated I/O
Memory-Mapped I/O
Polling I/O
Virtual I/O
The primary limitation of Programmed I/O (PIO) is that the CPU:
Requires special I/O instructions.
Cannot detect I/O completion.
Spends most of its time continuously checking the status of the peripheral (busy-wait loop).
Can only transfer data one bit at a time.
What type of interrupt (trap) is generated by instructions or internal events like a system call or division by zero?
Hardware interrupt
Software interrupt (trap)
Timer interrupt
I/O interrupt
The functional group of bus lines that carries the actual data being transferred is:
Address Bus
Control Bus
Data Bus
I/O Bus
Modern high-speed interfaces like PCIe and USB favor which type of communication?
Serial
Parallel
Synchronous
Asynchronous
In the Four-Cycle Handshaking Protocol, which signal is asserted by the receiver to signal it has accepted the data?
Request (Data Valid)
Acknowledge (Data Accepted)
Write Enable
Bus Grant
Hardware components external to the CPU and main memory, which enable data input, output, and long-term storage, are generically called:
Device Drivers
Peripherals
Controllers
Bus Masters
A hardware component (often a chip) that manages the communication between the CPU and the peripheral device is called a:
DMA Controller
Interrupt Handler
Device Controller
I/O Register
Devices such as Hard Disk Drives (HDD) and Solid State Drives (SSD) primarily function as non-volatile memory and are categorized as:
Input Peripherals
Output Peripherals
Storage Peripherals
Network Peripherals
The main benefit of Direct Memory Access (DMA) is that it manages data transfers directly between the I/O device and main memory by:
Bypassing the CPU
Increasing the CPU clock speed
Using only Programmed I/O
Eliminating the need for a Device Controller
The protocol specifically designed for high-speed SSDs connected via the PCI Express (PCIe) bus is:
SATA III
PATA
USB 3.0
NVMe (Non-Volatile Memory Express)
A processor containing dozens or hundreds of simpler cores, focused on massive parallelism (e.g., GPUs), is known as a:
Multi-Core Processor
Many-Core Processor
Symmetric Multiprocessor
Asymmetric Multiprocessor
A multiprocessing system where identical processors share the same memory and a single OS instance manages all processors is called:
Asymmetric Multiprocessing (AMP)
Distributed Multiprocessing
Symmetric Multiprocessing (SMP)
Heterogeneous Computing
In a Shared Memory Architecture, how does communication between cores primarily occur?
Through shared memory.
Through message passing.
Through network packets.
Through direct electrical signaling.
Which architecture is characterized by different processors with specific master/slave roles and is often used in embedded systems?
Asymmetric Multiprocessing (AMP)
Symmetric Multiprocessing (SMP)
Multi-threading
Shared Memory
The technique where a single core executes multiple threads, and the threads share resources but operate independently, is known as:
Instruction-level parallelism
Process-level parallelism
Multi-threading
Simultaneous Multi-Core
Relative to a CPU, a GPU architecture is characterized by:
Few cores optimized for sequential tasks.
Complex control logic and a large cache.
Hundreds/thousands of simpler cores.
Being optimized for single-stream execution.
A common challenge of concurrency where two or more threads attempt to access and modify shared data simultaneously is called a(n):
Deadlock
Race Condition
Bus Contention
Synchronization Miss
A system in which components located on networked computers communicate and coordinate their actions is formally defined as a:
Client-Server System
Peer-to-Peer System
Distributed System
Cloud Computing System
Which architecture is decentralized, where each node acts as both a client and a server, and is used in blockchain systems?
Client-Server Architecture
Peer-to-Peer (P2P) Architecture
Centralized System
Mesh Topology
Which network topology connects all nodes to a single, central hub or switch?
Bus Topology
Ring Topology
Mesh Topology
Star Topology
The mechanism that ensures a system continues to operate correctly even when one or more components fail is known as:
Load Balancing
Scalability
Fault Tolerance
Centralized Control
Cache memory is generally slower than main memory (RAM).
True
False
The goal of the Memory Hierarchy is to provide a fast, large, and inexpensive memory system.
True
False
A Cache Miss occurs when the requested data is not found in the cache, resulting in a slower access to the next memory level.
True
False
Set-Associative Cache pros include being simple and fast to implement, with no complex logic needed to find a spot. (This is a pro of Direct-Mapped).
True
False
Virtual memory allows for running programs that are larger than the available physical memory.
True
False
In Interrupt-Driven I/O, the CPU polls the status register of the I/O device in a tight loop. (This describes PIO).
True
False
Instructions: Write 'T' if the statement is true and 'F' if the statement is false. 7. The three functional groups of bus lines are Data Bus, Control Bus, and Instruction Bus. (The third is Address Bus).
True
False
The hierarchy of efficiency for I/O techniques is generally PIO ≪ Interrupt ≪ DMA.
True
False
The width of the Address Bus determines the number of bits transferred simultaneously.
True
False
DMA is generally more efficient than interrupts for small, time-sensitive events. (Interrupts are better for small, time-sensitive events).
True
False
A Non-Maskable Interrupt (NMI) is a hardware interrupt with the lowest priority, usually for minor errors. (It is the highest priority, for catastrophic errors).
True
False
SATA is a parallel transfer method that offers higher speeds than its legacy PATA predecessor. (SATA is a serial transfer method).
True
False
The DMA controller issues a single interrupt to the CPU after the entire data transfer is complete.
True
False
Performance monitoring tools aim to identify the component with 100% utilization while others wait, as this is the bottleneck.
True
False
An Output Peripheral is defined as a device that receives data from the computer and displays or presents it.
True
False
AMP systems generally offer higher scalability than SMP systems.
True
False
Distributed Memory Architecture simplifies the programming model and data sharing compared to Shared Memory.
True
False
One benefit of multi-threading is improved CPU utilization and reduced idle time.
True
False
The CPU architecture is generally optimized for sequential tasks, while the GPU is designed for parallel operations (SIMD model).
True
False
The memory hierarchy level that holds data and instructions currently being processed by the CPU is the (a) .
The key data structure in main memory used by the MMU for virtual-to-physical address translation is the (a) .
When an item is referenced, the principle of (a) suggests it will tend to be referenced again soon.
DRAM is built using a single (a) and a single capacitor.
The technique where an external device (like a disk drive) signals the CPU to stop current execution and handle an event is called an (a) .
The (a) contains lines for timing and control signals, such as Read/Write requests.
In the context of I/O, (a) refers to the CPU continuously checking the status register of the peripheral.
The interface standard that has largely replaced legacy PATA by using a serial transfer method is (a) .
The key data transfer process that bypasses the CPU and is managed by a specialized controller is (a) .
The communication mechanism used in a Distributed Memory Architecture is (a) .
The phenomenon where the physical limits of transistor scaling forced the industry to focus on parallel processing rather than single-core speed increases is related to (a) .
The benefit of multi-threading that leads to quicker handling of external operations is (a) .
The arrangement that defines the physical or logical arrangement of network nodes and affects performance, reliability, and scalability is the (a) .
The type of computing that involves processing data near the source (e.g., IoT devices) to reduce latency is (a) .
The primary goal of a Distributed System is to achieve resource sharing, scalability, reliability, and (a) .
Compare and contrast Symmetric Multiprocessing (SMP) and Asymmetric Multiprocessing (AMP), detailing the fundamental differences in their architecture, task distribution, and scalability.
Describe the role and mechanism of Direct Memory Access (DMA) in I/O operations, explaining why it is necessary and how it improves system efficiency compared to Programmed I/O (PIO) or Interrupt-Driven I/O for large data transfers.
