NEW
Font size
WorksheetsKiến trúc máy tính
Total questions: 62
Worksheet time: 31mins
What is computer architecture mainly related to?
The physical components of a computer
How to write programs
The visible properties for programmers
Only storing data
What does computer organization focus on?
Instruction set design
Details of hardware implementation
Programming languages
User interface
Among the basic functions of a computer, which function is NOT?
Data processing
Data storage
Data movement
Data encryption
Which component controls the operation of the computer?
Main memory
ALU
Control unit
I/O module
Which component temporarily stores data inside the CPU?
Cache memory
Registers
Hard drive
Main memory
What is the main idea of von Neumann architecture?
Parallel execution
Stored program concept
Multiple processors
Distributed memory
In the IAS computer, where are instructions and data stored?
Separate memory
Only cache memory
Main memory
Registers
Which register holds the address of the next instruction?
IR
MAR
PC
MBR
What does the Instruction Register (IR) store?
Data from memory
Address of the instruction
Current instruction
Result of the operation
Which generation of computers used vacuum tubes?
First generation
Second generation
Third generation
Fourth generation
In which generation was the transistor introduced?
First generation
Second generation
Third generation
Fourth generation
Which generation does the integrated circuit (IC) belong to?
First generation
Second generation
Third generation
Fifth generation
Moore's Law states that:
The clock speed doubles every year
The memory size doubles every year
The number of transistors doubles per cycle
Power consumption is halved every year
What factor limits the increase in clock speed?
Instruction
Power and heat
Buffer size
Software
CPI stands for:
Cycle on command
Cost per command
Control program index
Central processing interface
Which formula represents execution time?
T = CPI × Clock frequency
T = Number of instructions / CPI
T = Number of instructions × CPI × Clock cycle time
T = Clock frequency / CPI
Which architecture uses multiple cores on a chip?
Single core
Multi-core
Distributed
Sequential
The most suitable task for a GPU is:
Sequential tasks
Control operations
Parallel data processing
File management
What does CISC emphasize?
Simple instructions
Reduced instruction set
Complex instructions
Parallel execution
What is a main feature of the x86 architecture?
Based on RISC
Backward compatibility
Single instruction format
Fixed-length instructions
Embedded systems are designed to:
Run multiple programs
Perform a dedicated function
Replace desktop computers
Support gaming
What is a typical constraint of embedded systems?
Unlimited memory
High power consumption
Real-time feedback
Large screen
The ARM processor is famous for:
High power consumption
CISC architecture
Low power consumption
Large instruction set
What is the purpose of performance tests?
Improve hardware
Measure performance
Store data
Control execution
The SPEC tests are primarily used to:
Test graphics
Measure processor performance
Design hardware
Compile programs
Amdahl's law describes what?
Memory performance
Instruction execution
Limits of parallel speedup
Cache efficiency
Little's Law relates to:
Buffer size and speed
Arrival rate and response time
Command mix
Clock speed
Which bus carries the memory address?
Data bus
Control bus
Address bus
System bus
Which bus controls the timing and operations?
Data bus
Control bus
Address bus
I/O bus
What is DMA mainly used for?
Decoding instructions
Controlling the CPU
Direct I/O–memory transfer
Buffer management
What happens in the fetch cycle?
Execute the command
Decode the command
Fetch the command from memory
Store the result
What is the purpose of interrupts?
Stop the CPU permanently
Improve graphics
Handle external events
Increase clock speed
Which interrupt is generated by I/O devices?
Program interrupt
Timer
What are interrupts used for:
To stop the CPU permanently
To improve graphics
To handle external events
To increase clock speed
Which interrupt is generated by I/O devices?
Program interrupt
Timer interrupt
I/O interrupt
Hardware interrupt
What is the main disadvantage of a shared bus?
High cost
Low scalability
Complex design
High latency memory
Connecting point to point improves:
Power consumption
Software efficiency
Bandwidth and scalability
Command decoding
What data transmission method does QPI use?
Parallel signal
Shared bus
Packet-based transmission
Analog signal
How is PCI Express best described?
Shared bus
Point-to-point serial connection
Parallel bus
Memory-only interface
The PCIe transaction layer is responsible for:
Electrical signals
Error correction
Creating and processing requests
Routing paths
Which layer handles error detection in PCIe?
Physical layer
Data link layer
Transaction layer
Application layer
Which statement is CORRECT?
The speed of the clock alone determines performance
Multi-core always doubles performance
Architecture and organization both affect performance
Software has no impact on performance
Which component performs arithmetic and logic operations?
Control unit
Main memory
ALU
I/O module
Which component provides communication between the CPU, memory, and I/O?
Buffer
Registers
System bus
Control unit
Computer organization is more concerned with:
What computers do
How computers are programmed
How computers are built
How users interact with computers
Which register holds data to be written to or read from memory?
PC
IR
MAR
MBR
What happens after the fetch stage in the instruction cycle?
Store
Decode
Interrupt
Stop
Which register stores the address of the memory being accessed?
PC
IR
MAR
AC
What type of interrupt is generated by division by zero?
Timer interrupt
I/O interrupt
Program interrupt
Hardware interrupt
Why are interrupts important?
They stop program execution
They improve CPU speed
They allow the CPU to respond to events
They increase memory size
Which bus determines the number of bits that can be transmitted at one time?
Control bus
Address bus
Data bus
System bus
Increasing the width of the data bus mainly improves:
Memory size
Data transmission speed
Instruction set
Energy efficiency
Which bus carries command signals and timing?
Data bus
Address bus
Control bus
Expansion bus
What is the main limitation of a single shared bus architecture?
High cost
Low reliability
Bus content
Complex software
What is the main advantage of multi-bus systems?
Lower cost
Better scalability and performance
Simpler design
Less hardware
Which type of connection replaces traditional shared buses?
Parallel bus
System bus
Point-to-point connection
Address bus
QPI stands for:
Fast parallel interface
Fast path connection
Quality performance interface
Queue path connection
Which QPI layer handles packet routing?
Physical layer
Link layer
Routing layer
Protocol layer
PCI Express transmits data using:
Parallel signals
Shared wires
Serial lanes
Optical signals
Which PCIe layer is responsible for flow control and error detection?
Transaction layer
Data link layer
Physical layer
Application layer
The main benefit of serial connections like PCIe is what?
Simpler software
Lower clock speeds
Higher bandwidth and scalability
Larger instruction sets
Which statement best describes overall system performance?
It only depends on CPU speed
It only depends on memory
It is affected by CPU, memory, and connectivity
It only depends on software
