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NAND Gates, CPU Basics, and Networking Worksheet (Grade 13)

Total questions: 60

Worksheet time: 30mins

Name
Class
Date
1.

Which is a basic logic gate from which all Boolean functions can be derived?

a)

AND

b)

NAND

c)

OR

d)

XOR

2.

What correctly describes a NAND gate's output when both inputs are 1?

a)

0

b)

1

c)

Complement of AND output

d)

Same as OR output

3.

Which statement correctly describes NAND gates' universal property?

a)

Can implement AND function

b)

Can implement OR function

c)

Any combinational circuit can use only NAND

d)

Cannot implement NOT function

4.

For F = (A·B)' implemented with only NAND gates, which is valid?

a)

Single 2-input NAND with inputs A and B

b)

AND gate followed by NOT gate

c)

Two NAND gates in series

d)

Three NAND gates in specific configuration

5.

To implement XOR using only NAND gates, which would work?

a)

Four NAND gates in specific arrangement

b)

Three NAND gates with clever connections

c)

Two NAND gates directly connected

d)

Five NAND gates with redundancy

6.

When simplifying Boolean expressions for NAND-only implementation, which step is essential?

a)

Convert to Sum-of-Products form

b)

Apply De Morgan's Theorem

c)

Double invert the expression

d)

Convert to Product-of-Sums form first

7.

A circuit uses 5 NAND gates but could use 3. What likely caused inefficiency?

a)

No Boolean simplification applied

b)

Redundant inverters using NAND gates

c)

Function inherently requires 5 gates

d)

Direct translation without optimization

8.

Comparing XOR implementation with NAND vs. NOR gates, which is accurate?

a)

NAND typically uses fewer gates

b)

Depends on available IC chips (7400 vs 7402)

c)

NOR is generally more efficient

d)

Both require same number of gates

9.

Two implementations: A uses 8 NAND gates (12ns delay); B uses 6 NOR + 2 inverters (15ns delay). Which justifies choosing the slower option?

a)

B consumes less power

b)

B uses fewer transistors

c)

NOR ICs are cheaper

d)

B has more regular layout

10.

Which is a CPU component?

a)

Arithmetic Logic Unit

b)

Control Unit

c)

Main Memory

d)

Registers

11.

What is a primary stage in the CPU instruction cycle?

a)

Fetch

b)

Store to Disk

c)

Decode

d)

Write Back

12.

How does multi-core improve performance vs single-core at the same clock speed?

a)

Allows parallel instruction execution

b)

Increases individual core clock speed

c)

Enables better multitasking with threads

d)

Reduces power per instruction

13.

Which correctly distinguishes Computer Architecture from Organization?

a)

Architecture defines ISA; Organization implements it

b)

Including multiply instruction is architectural

c)

Cache size is organizational

d)

Architecture deals with logic circuits; Organization with user features

14.

CPU at 3.0 GHz with CPI of 4. Which correctly calculates MIPS?

a)

MIPS = (3.0×109)/(4×106)(3.0 \times 10^9) / (4 \times 10^6)

b)

MIPS = 3000 / 4

c)

MIPS = 750

d)

(1/(4×3.0×109))/106(1 / (4 \times 3.0 \times 10^{-9})) / 10^{6}

15.

For a low-power embedded device, which processor feature should be prioritized?

a)

High clock speed (>4 GHz)

b)

Simple RISC instruction set

c)

Large L3 cache

d)

Advanced power management states

16.

CPU X uses CISC; CPU Y uses RISC. Both target similar performance. Which is likely true?

a)

X has more complex control logic

b)

Y relies more on compiler optimization

c)

X has higher CPI

d)

Y has longer, more complex instructions

17.

System bottlenecks on slow memory access. Which directly helps?

a)

Increasing CPU clock speed

b)

Adding larger/faster cache

c)

Implementing deeper pipeline

d)

Using faster DRAM technology

18.

Choosing between integrated GPU vs separate CPU+GPU: which favors integration?

a)

Lower system cost and power

b)

Higher peak graphics performance

c)

Better thermal management

d)

Reduced motherboard space

19.

What is an essential network component?

a)

At least two devices

b)

Shared CPU

c)

Communication medium

d)

Shared resources/information

20.

What is a primary purpose of business networks?

a)

Sharing information/files

b)

Sharing hardware resources

c)

Isolating computers for security

d)

Facilitating communication

21.

In client-server model, which is correct?

a)

Server controls resource access

b)

Client grants access to server resources

c)

Both client and server have equal control over shared resources

d)

Access decisions are made by the network switch

22.

Which is a peer-to-peer network characteristic?

a)

No dedicated central server

b)

More scalable for thousands of users

c)

Centralized security management

d)

Computers act as both clients and resource providers

23.

Small office with 5 computers needs shared printing and files. Which setup is valid?

a)

Dedicated Windows Server

b)

Peer-to-peer workgroup

c)

All computers and printer to switch with file sharing

d)

Printer connected to one computer and shared

24.

For managing sensitive payroll data, which practice is essential?

a)

Store on central server with access controls

b)

Place in shared folder for all employees

c)

Encrypt data during transmission

d)

Include regular backups

25.

Shared printer bottlenecks with large documents. Which solution works?

a)

Install dedicated print server with more memory

b)

Implement print queue management

c)

Increase file server clock speed

d)

Move printer to separate network segment

26.

Compared to "sneakernet," what is a network advantage?

a)

No physical media movement

b)

Guaranteed 100% accuracy

c)

Near-instant sharing over distance

d)

Inherently higher security

27.

Choosing one network laser printer versus personal inkjets for 20 employees. Which supports shared printing?

a)

Lower total cost of ownership

b)

Higher print quality for all documents

c)

Better resource utilization

d)

Faster print speed for each user

28.

Which is an input device?

a)

Mouse

b)

Monitor

c)

Scanner

d)

Printer

29.

What defines a pointing device?

a)

Controls cursor position

b)

Used for text entry

c)

Provides tactile feedback

d)

Examples: mouse, trackball, touchscreen

30.

How does LCD differ from CRT?

a)

Thinner, lighter, less power

b)

Uses cathode ray tube

c)

CRT has better color/viewing angles

d)

LCD suffers from flicker at low refresh

31.

For a graphics design studio, which I/O device is critical?

a)

High-resolution color-accurate monitor

b)

High-speed dot-matrix printer

c)

Large-format scanner/digitizing tablet

d)

Basic keyboard and optical mouse

32.

For printing architectural blueprints, which is essential?

a)

High-resolution laser printer

b)

Large-format plotter

c)

Ability to print on roll paper (A1/A0)

d)

50 pages/minute speed

33.

Why are shared network lasers more cost-effective than individual inkjets?

a)

Lower inkjet initial cost

b)

Higher inkjet per-page cost

c)

Laser reliability and duty cycle

d)

Laser photorealistic image quality

34.

Comparing QWERTY vs Dvorak keyboards, which is true?

a)

QWERTY designed to slow typists

b)

Dvorak increases speed, reduces movement

c)

Dvorak is most common default

d)

QWERTY dominance due to familiarity

35.

School choosing between COM (microfilm) versus laser printers for archiving. When is COM better?

a)

Extremely high volume (thousands daily)

b)

Limited long-term storage space

c)

Frequent need for photocopies

d)

Must be readable without special viewer

36.

Which gate is considered a universal gate?

a)

NAND

b)

AND

c)

OR

d)

XOR

37.

De Morgan's Law states that:

a)

(A+B)=AB (A + B)' = A' \cdot B'

b)

(AB)=A+B (A \cdot B)' = A' + B'

c)

A+B=(AB) A + B = (A' \cdot B')'

d)

AB=(A+B) A \cdot B = (A' + B')'

38.

To implement an AND gate using only NAND gates, you need:

a)

One NAND gate

b)

Two NAND gates

c)

Three NAND gates

d)

Four NAND gates

39.

The Control Unit (CU) in a CPU is responsible for:

a)

Performing arithmetic operations

b)

Decoding instructions

c)

Generating control signals

d)

Managing data flow between CPU components

40.

Which factor affects CPU performance?

a)

Clock speed

b)

Cache size

c)

Number of cores

d)

Instruction set architecture

41.

In a RISC processor, which is typical?

a)

Large set of complex instructions

b)

Load/store architecture

c)

Fixed-length instructions

d)

Microcode implementation

42.

Which is an advantage of a server-based network over peer-to-peer?

a)

Centralized security management

b)

Lower cost

c)

Better scalability

d)

No need for dedicated hardware

43.

Network backups are important because:

a)

They prevent hardware failure

b)

They allow recovery from data loss

c)

They improve network speed

d)

They are required by law in some industries

44.

Which is an example of a network peripheral?

a)

Shared printer

b)

Network-attached storage (NAS)

c)

USB flash drive

d)

Network scanner

45.

Which is an advantage of laser printers over inkjet printers?

a)

Lower cost per page

b)

Better for photo printing

c)

Faster printing speed

d)

More reliable for high-volume printing

46.

A touchscreen is an input device that:

a)

Can be used without a separate pointing device

b)

Detects finger or stylus contact

c)

Is only available in resistive technology

d)

Is commonly used in smartphones and tablets

47.

Which statement about monitors is true?

a)

Resolution is measured in pixels

b)

Refresh rate is measured in Hertz (Hz)

c)

CRT monitors are thinner than LCD monitors

d)

Response time affects motion blur

48.

Optical Character Recognition (OCR) is used to:

a)

Read handwritten text

b)

Convert printed text into digital text

c)

Read barcodes

d)

Recognize faces

49.

To implement an OR gate using only NAND gates, how many NAND gates are needed?

a)

One NAND gate

b)

Two NAND gates

c)

Three NAND gates

d)

Four NAND gates

50.

The expression (ABC)(A \cdot B \cdot C)' can be implemented using:

a)

A single 3-input NAND gate

b)

Two 2-input NAND gates

c)

Three 2-input NAND gates

d)

A 2-input NAND gate and an inverter

51.

In a combinational circuit, which is a valid method to check for hazards?

a)

Analyze the Karnaugh map for adjacent minterms not covered by the same prime implicant

b)

Simulate with all possible input transitions

c)

Check only the critical path

d)

Ignore timing considerations

52.

When designing sequential circuits, which flip-flop is commonly used?

a)

D flip-flop

b)

JK flip-flop

c)

T flip-flop

d)

SR latch

53.

In microprocessor architecture, which is a characteristic of Harvard architecture?

a)

Separate memory for instructions and data

b)

Can fetch instructions and data simultaneously

c)

Simpler bus structure

d)

Lower performance than Von Neumann

54.

Which technique is used for processor performance optimization?

a)

Pipelining

b)

Branch prediction

c)

Speculative execution

d)

Increasing only clock speed

55.

The OSI model consists of how many layers?

a)

5 layers

b)

7 layers

c)

4 layers

d)

8 layers

56.

Which is a function of the Transport layer in the OSI model?

a)

End-to-end connection management

b)

Error recovery

c)

Physical addressing

d)

Flow control

57.

In virtual memory systems, which is a benefit of paging?

a)

Eliminates external fragmentation

b)

Allows programs larger than physical memory

c)

Simplifies memory allocation

d)

Reduces memory access time

58.

Which I/O handling method allows the CPU to perform other tasks during I/O operations?

a)

Interrupt-driven I/O

b)

Direct Memory Access (DMA)

c)

Programmed I/O

d)

Memory-mapped I/O

59.

Which is an advantage of interrupt handling in I/O operations?

a)

CPU doesn't need to poll devices

b)

Better CPU utilization

c)

Faster response to I/O events

d)

Simpler programming model

60.

In assembly language, which is a valid use of the MOV instruction?

a)

MOV AX, BX

b)

MOV [BX], AX

c)

MOV AX, 5

d)

MOV CS, AX