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WorksheetsCOA CHAP 1.2
Total questions: 107
Worksheet time: 54mins
Which statement best describes the role of a transistor in digital circuits?
It measures analog voltages continuously
It amplifies audio for output speakers
It switches states to represent 0 and 1
It stores long-term programs and instructions
Integrated circuits are primarily built from which basic component?
Transistors combined together
Inductors for magnetic storage
Resistors forming voltage dividers
Capacitors arranged in arrays
What mathematical system underpins the operation of digital logic gates?
Vector calculus and matrices
Numerical methods calculus
Probability theory models
Boolean algebra principles
Who proposed the basic principles of Boolean algebra in 1854?
Gottfried Leibniz in 1703
Claude Shannon in 1948
George Boole in 1854
Alan Turing in 1936
Which researcher connected Boolean algebra to relay-switching circuit design?
Herman Hollerith suggested punched cards
Claude Shannon suggested relay use
Norbert Wiener proposed cybernetics
John von Neumann built stored programs
Why is Boolean algebra considered a convenient tool in digital design?
It eliminates the need for timing diagrams
It provides economical analysis and design
It ensures analog linearity in circuits
It replaces hardware with optical fibers
In Boolean logic, what values can a variable take?
Complex numbers with phases
Binary values 0 or 1
Only positive real numbers
Any integer from −1 to 1
Which condition makes the AND operation yield true?
Both inputs are false
Either input is true
Exactly one input is true
Both inputs are true
When parentheses are omitted, which operation takes precedence in Boolean expressions?
OR takes precedence by default
NOT takes lowest precedence
XOR overrides all others
AND takes precedence by default
Which statement about representing the AND operation is correct when no ambiguity occurs?
It must use a plus sign symbol
It can be shown by simple concatenation
+ denotes dot-free concatenation
It requires the exclusive OR mark
What is the defining behavior of the OR operation in Boolean logic?
True exactly when inputs are unequal
True only when both inputs are false
True when either or both inputs are true
True only when both inputs are true
What effect does the NOT operation have on its operand?
It inverts the operand’s value
It leaves the operand unchanged
It compares two operand values
It doubles the operand’s value
Which Boolean operator yields 1 only when both inputs P and Q are 1?
XOR operator with inputs P and Q
AND operator with inputs P and Q
OR operator with inputs P and Q
NOR operator with inputs P and Q
For inputs P=0 and Q=1, what is the output of P XOR Q?
0 because inputs are different
1 because inputs are different
1 because inputs are same
0 because inputs are same
Which gate outputs 0 only when both inputs are 1?
XOR gate with two inputs
NOR gate with two inputs
NAND gate with two inputs
AND gate with two inputs
The output of a two-input NOR gate is 1 when:
Any input is 1
Both inputs are 1
Both inputs are 0
Inputs are different
Extend XOR to more than two inputs. When is the multi-input XOR equal to 1?
When an odd number of inputs are 1
When all inputs are 1
When no inputs are 1
When any input is 1
Which identity matches the statement: A + B = B + A?
Identity Law for addition
Associative Law for addition
Distributive Law for addition
Commutative Law for addition
Which identity states that A • (B + C) = (A • B) + (A • C)?
DeMorgan's Theorem
Commutative Law of multiplication
Distributive Law of multiplication over addition
Associative Law of multiplication
What is the value of A • Ā according to basic postulates?
1 by inverse elements
0 by inverse elements
A by identity elements
Ā by inverse elements
Using identity elements, what is 1 • A equal to?
1 by identity element
A by identity element
0 by identity element
Ā by identity element
According to DeMorgan's Theorem, what is the complement of A • B?
A + B̄
Ā + B̄
Ā • B̄
Ā + B
Evaluate P NAND Q when P=1 and Q=0.
0 because both are 1
1 because not both are 1
0 because inputs differ
1 because both are 0
Which statement correctly describes the multi-input AND operation?
Output is 1 if all inputs are 0
Output is 1 if inputs are different
Output is 1 if all inputs are 1
Output is 1 if any inputs are 1
Choose the correct associative law for OR.
(A + B) = B + (A • C)
A + (B • C) = (A + B) + C
A • (B • C) = (A + B) • C
A + (B + C) = (A + B) + C
Which operation yields 0 when any input is 1 for all inputs?
XOR with multiple inputs
NAND with multiple inputs
NOR with multiple inputs
OR with multiple inputs
If P=1 and Q=1, what is the output of P XOR Q?
0 because inputs are identical
1 because inputs are opposite
1 because inputs are identical
0 because inputs are opposite
Which gate outputs 1 only when both inputs A and B are 1?
XOR gate
AND gate
OR gate
NOR gate
For a NOT gate, if input A = 0, what is the output F?
F = A + 1
F = 1
F = A
F = 0
Which algebraic expression matches the NOR gate output shown in the table?
F = (A + B)'
F = AB
F = A + B
F = A ⊕ B
According to the XOR truth table, when A = 1 and B = 0, what is F?
F = 0
F = B'
F = 1
F = A
From the NAND uses diagram, which single gate is created by tying both inputs of a NAND together to input A?
XOR gate
OR gate
NOT gate
Buffer gate
In the NAND implementation where two NANDs feed a final NAND, what function does the overall circuit perform?
A + B
(A • B)'
A • B
A ⊕ B
Which truth table row for NAND is correct based on the basic gate panel?
A=1, B=1 ⇒ F=1
A=0, B=0 ⇒ F=0
A=1, B=0 ⇒ F=1
A=0, B=1 ⇒ F=0
On the NOR uses page, connecting both inputs of a NOR to A realizes which function?
A
A + B
A'
AB
The NOR-only circuit that first NORs A and B together, then NORs with a second gate implements what overall function?
A + B
(A + B)'
A • B
(A • B)'
Which statement best explains why NAND and NOR are called universal gates?
They can implement any logic function
They only output 1 for unique inputs
They are faster than XOR in all cases
They have the fewest inputs always
Which statement best defines a combinational circuit?
Output depends only on current inputs
Output depends on stored past inputs
Output toggles at fixed clock edges
Output cycles through preset sequence
In a combinational circuit, what primarily causes delay between input change and output change?
Clock distribution delays
Wire inductance resonance
Gate propagation delays
Flip-flop setup delays
A combinational block is described as having n binary inputs and m binary outputs. What does this imply?
There are n inputs mapping to m outputs
There are m inputs mapping to n outputs
Each output feeds back to inputs
Each input stores m past values
Which is NOT one of the three common ways to specify a combinational circuit?
State transition diagram
Truth table representation
Graphical gate symbols
Boolean equation form
For a truth table with three inputs A, B, C, how many possible input combinations exist?
Nine combinations total
Eight combinations total
Four combinations total
Six combinations total
Given a truth table for F(A,B,C), the sum-of-products (SOP) implementation is built by summing which terms?
Minterms where F equals 1
Maxterms where F equals 0
All possible minterms
Maxterms of each input
In product-of-sums (POS) form, F is expressed as a product of which items?
Differences of binary inputs
Exclusive sums of inputs
Maxterms corresponding to zeros
Minterms corresponding to ones
Which representation directly lists F for every input combination without algebraic symbols?
Timing waveform diagram
Gate-level schematic
Boolean equation form
Truth table representation
Which advantage is typical of algebraic simplification before implementing SOP or POS?
Reduces gate count and inputs
Increases fan-in requirements
Forces unique circuit layout
Eliminates need for truth tables
In the shown SOP network for F(A,B,C), multiple AND gates feed an OR gate. What do the inputs to each AND gate represent?
A specific minterm of A,B,C
A specific maxterm of A,B,C
A parity of the variables
A half-sum of two variables
If a truth table for F has ones at minterms m1, m3, m6, m7 only, which is the correct canonical SOP?
F = Σ m(1,3,6,7)
F = Π M(1,3,6,7)
F = Σ M(1,3,6,7)
F = Π m(1,3,6,7)
A designer chooses POS instead of SOP for a function with many zeros and few ones. Which reason best supports this choice?
POS ensures hazard-free outputs automatically
POS avoids needing any inverters entirely
POS uses fewer terms when zeros dominate
POS guarantees minimal gate depth always
In a product-of-sums implementation, which gate type typically combines the outputs of several OR gates to produce the final function F?
A single AND gate after OR stages
A single OR gate after AND stages
A single NAND gate after OR stages
A single XOR gate after OR stages
The simplified implementation shown uses inputs A̅ and C̅ feeding one gate whose output and B feed a second gate to produce F. Which Boolean form best matches this circuit?
F = (A̅ + C̅) + B
F = (A̅ · C̅) + B
F = (A̅ + C̅) · B
F = (A̅ · C̅) · B
Algebraic simplification aims to do which of the following when reducing a Boolean expression?
Introduce XOR operators for brevity
Enumerate all minterms exhaustively
Use identities to reduce elements
Convert to Gray code before mapping
In the product-of-sums network for three variables A, B, C feeding multiple OR gates whose outputs are combined, each OR gate most likely represents which of the following?
A Karnaugh map adjacency group
A minterm corresponding to F=1 case
A consensus term added for hazard
A maxterm corresponding to F=0 case
For a one-digit packed decimal incrementer, the inputs A, B, C, D represent a BCD digit. Which input combination is considered a “don’t care” in standard BCD?
0000 to 1111 inclusive
0101 to 1000 inclusive
0000 to 1001 inclusive
1010 to 1111 inclusive
Suppose a BCD input 0111 (7) is applied to the incrementer. Which binary-coded output should represent the incremented value?
0110 for eight
1000 for eight
0111 for eight
1001 for eight
Which step distinguishes the Quine–McCluskey method from purely algebraic simplification when minimizing Boolean functions?
Tabulating and combining minterms by bit count
Using XOR-based parity groupings primarily
Drawing only gate-level schematics first
Applying DeMorgan’s laws exclusively
When implementing F = (A̅ + C̅) · B in gates, what is the minimum two-level structure that realizes F?
One NAND of A and C feeding an OR with B
One NOR of A and C feeding an AND with B
One AND gate for A̅ and C̅ feeding an OR with B
One OR gate for A̅ and C̅ feeding an AND with B
In a 4-to-1 multiplexer, which data input is routed to the output when S2=0 and S1=1?
D0
D1
D2
D3
How many select lines are required for an n-to-1 multiplexer when n=8?
1 select line
2 select lines
3 select lines
4 select lines
8 select lines
Which statement best describes a decoder in digital logic?
Converts binary code into one active output line
Combines many outputs into a single input line
Stores binary words for later retrieval
Converts multiple inputs into one output line
A 3-to-8 decoder has inputs A2 A1 A0. When A2A1A0=101, which output is active (assuming active-high outputs)?
Y3 becomes high
Y5 becomes high
Y7 becomes high
Y6 becomes high
Which component can implement a demultiplexer function most directly?
Register with parallel load
Decoder with enable used as data
Encoder with priority disabled
Multiplexer with enable tied low
In address decoding for memory-mapped I/O, what is the purpose of the decoder?
Stores the current address permanently
Selects one device for a given address
Generates clock signals for buses
Converts data to serial format
According to the 4-to-1 multiplexer truth table, which selection maps input D3 to output F?
S2S1 = 00
S2S1 = 01
S2S1 = 10
S2S1 = 11
Which is a correct comparison between a multiplexer and a decoder?
Multiplexer stores data; decoder transmits data
Multiplexer selects one input; decoder selects one output
Multiplexer decodes binary code; decoder encodes inputs
Multiplexer increases outputs; decoder reduces outputs
A 4-to-1 MUX is used to route sensor data. If S2S1 toggles through 00,01,10,11, what sequence appears at F? Assume stable inputs D0..D3.
D0, D0, D2, D2
D1, D0, D3, D2
D0, D1, D2, D3
D3, D2, D1, D0
For address decoding using a 4-to-16 decoder with active-high outputs, which condition ensures only one memory chip is enabled at a time?
Drive decoder with data bus lines
Short all outputs together directly
Use unique address ranges on inputs
Tie all enables low and share outputs
Which statement best defines Read-Only Memory (ROM) in digital logic?
A register that updates on every clock
A sequential circuit with feedback loops
A device for temporary arithmetic storage
A memory storing permanent binary information
Why is ROM considered a combinational circuit rather than a sequential circuit?
Its outputs depend only on present inputs
It continuously changes with clock edges
It stores data using flip-flop feedback
It requires refresh cycles like DRAM
What does the read operation in ROM involve?
Selecting an address to produce stored bits
Writing new data into chosen locations
Shifting bits through a serial port
Clearing all contents before accessing
Which phrase best characterizes the contents of ROM?
Permanent binary information
Volatile cache-based patterns
Analog calibration waveforms
Frequently updated micro-ops
When modeled as a combinational circuit, a ROM maps:
Address inputs to fixed output words
Clock pulses to changing states
Enable lines to internal latches
Data inputs to writable registers
Which outcome is expected if the same ROM address is applied repeatedly?
The same fixed word appears each time
Different words cycle on each attempt
No output until a write completes
An analog level gradually drifts
Which is a valid reason to use ROM in a system design?
To provide volatile working memory
To buffer high-speed analog signals
To store firmware that must not change
To implement counters needing clocks
Consider a ROM with 10 address lines and 8 data output lines. Which statement is correct?
It holds 2048 words of 4 bits each
It holds 512 words of 16 bits each
It holds 8 words of 1024 bits each
It holds 1024 words of 8 bits each
Which statement best defines a sequential circuit?
Output depends only on clock frequency
Output depends only on current inputs
Output depends on current and past inputs
Output depends only on internal power
Why are flip-flops considered the simplest sequential circuits?
They produce multiple parallel outputs
They implement pure combinational logic
They store one bit using two stable states
They require no input signals at all
A flip-flop is described as a bistable device. What does bistable mean in this context?
It has one stable state only
It has two stable states
It has three transient states
It never reaches a stable state
Which feature of flip-flops enables them to act as 1-bit memory elements?
Dependence on past inputs exists
Asynchronous propagation delays occur
Two complementary outputs exist
Multiple input lines are used
In the absence of further input, what does a flip-flop do?
It resets automatically to zero state
It remains in its current stable state
It outputs undefined metastable state
It toggles continuously between states
Which pair correctly describes the outputs of a flip-flop?
Both outputs equal the same value
One output is random noise
Outputs are complements of each other
Outputs are independent analog levels
Which characteristic distinguishes sequential circuits from combinational circuits most clearly?
Generation of analog instead of digital signals
Dependence on present and past inputs
Use of only logic gates without memory
Requirement of no power for operation
A system uses combinational logic plus a 1-bit memory element to control state transitions. Which component most appropriately provides that 1-bit memory?
Half adder without storage
Flip-flop with complementary outputs
Decoder with enable input
Priority encoder module
In the S-R latch characteristic table, what is the next state Q(n+1) when inputs S=0 and R=0, assuming current state Q(n)=1?
Undefined due to invalid inputs
1 because set is active
1 because state is held
0 due to reset dominance
For an S-R latch, which input combination leads to an undefined or invalid next state?
S=1, R=1
S=0, R=0
S=0, R=1
S=1, R=0
Using the S-R latch response table, if S pulses high at t=1 while R=0 and initial Q was 0, what is Q after the pulse?
Q becomes undefined then resets
Q toggles each clock
Q becomes 0 and stays 0
Q becomes 1 and stays 1
In the J-K flip-flop diagram, which statement best describes the role of the cross-coupled feedback to the inputs of the OR/NOR-like gates at the outputs?
It converts the device into a D latch
It enables toggling when J=K=1
It forces level-sensitive latching only
It disables the clocked gating path
When clock is active on the J-K flip-flop and J=1, K=0, what is the next state Q? Assume standard behavior.
Q becomes indeterminate
Q holds previous state
Q sets to 1
Q resets to 0
For the J-K flip-flop, what happens when J=K=1 during the active clock edge?
Q toggles to the opposite state
Q becomes high-impedance
Q becomes forced to 1
Q becomes forced to 0
In the 5-bit shift register diagram, what is the primary function of the chain of D flip-flops with a shared clock?
Parallel load of multiple words
Serial-to-parallel data shifting
Combinational decoding logic
Asynchronous memory refresh
If the serial input is 1,0,1,1,0 applied over five consecutive clock pulses to the 5-bit shift register initially cleared, what is the serial output after the fifth pulse?
1 because first bit has reached out
0 because register length is variable
1 because outputs always mirror inputs
0 because last stage just loaded 0
Which statement correctly distinguishes an S-R latch from the J-K flip-flop shown?
J-K cannot store previous state
J-K resolves S=R=1 by toggling
Latch requires a clock signal
Both are edge-triggered devices
A 5-bit shift register like the one shown is best used to implement which operation in digital systems?
Priority encoding of events
Analog-to-digital conversion
Time-delayed bit pipeline
Bitwise AND over five inputs
Which statement best defines a counter in digital logic?
A combinational circuit generating parity from inputs
A device that multiplies clock frequency using dividers
A memory that stores arbitrary binary words indefinitely
A register that increments by one modulo its capacity
What happens to the count value when a counter reaches its maximum capacity?
It resets to zero on the next increment
It holds the maximum until power is cycled
It decrements back to zero automatically
It pauses counting until a load signal
Why are asynchronous counters relatively slow compared with synchronous counters?
Each flip‑flop triggers the next, causing ripple delay
They depend on analog propagation through wires
They require higher clock frequencies to operate
They use more gates per flip‑flop than others
Which feature characterizes a synchronous counter?
All flip‑flops change state on the same clock
Only the first flip‑flop receives the clock input
The count resets only with asynchronous clear
Outputs toggle solely from combinational logic
In a CPU, which component is a practical example of a counter?
Status register storing condition code bits
Program counter advancing through instruction addresses
Arithmetic logic unit executing micro‑operations
General‑purpose register holding operand values
In the 8‑bit parallel register diagram labeled Ripple Counter, what do the lines labeled D01–D08 represent?
Parallel output lines from each flip‑flop stage
Individual clock inputs for each flip‑flop
Asynchronous clear lines daisy‑chained together
Data inputs tied to a serial shift register
Considering propagation delays, which design generally achieves higher maximum counting frequency?
Synchronous counter with common clocking
Asynchronous ripple counter chaining stages
Program counter using microcoded control
Ring oscillator built from inverters
Which term refers to any integrated circuit that can be configured by the end user to implement digital hardware designs?
Programmable Logic Device (PLD)
Programmable Logic Array (PLA)
Logic Block
Programmable Array Logic (PAL)
Which device has two programmable logic levels—an AND-plane and an OR-plane—both programmable?
Field-Programmable Gate Array (FPGA)
Programmable Array Logic (PAL)
Programmable Logic Array (PLA)
Complex PLD (CPLD)
Which device features a programmable AND-plane followed by a fixed OR-plane?
Programmable Array Logic (PAL)
Logic Block
Simple PLD (SPLD)
Programmable Logic Array (PLA)
A Simple PLD (SPLD) is best described as which of the following?
A multi-chip CPLD
A full FPGA fabric
A single logic block
A PLA or PAL device
Which statement best contrasts CPLDs and FPGAs in terms of logic resources?
Neither CPLDs nor FPGAs use input planes for resources
Both CPLDs and FPGAs offer equally wide input resources
FPGAs offer wider input resources; CPLDs offer narrower resources
CPLDs offer wider input resources; FPGAs offer narrower resources
Which device typically offers a higher ratio of flip-flops to logic resources?
Field-Programmable Gate Array (FPGA)
Complex PLD (CPLD)
Programmable Array Logic (PAL)
Programmable Logic Array (PLA)
In the context of FPGAs, what is a logic block most accurately described as?
A fixed OR-plane with gates
A complete microprocessor subsystem
A dedicated memory macrocell
A small circuit unit replicated in an array
