MCQ_VLSI

MCQ_VLSI

University

10 Qs

quiz-placeholder

Similar activities

NSTP-CWTS Final Quiz 2

NSTP-CWTS Final Quiz 2

University

15 Qs

Session 3

Session 3

University

13 Qs

Defense Expo Quiz

Defense Expo Quiz

University

10 Qs

GKA2043 Quiz 1

GKA2043 Quiz 1

University

10 Qs

PROFITABILITY RATIOS & MARKET TESTS

PROFITABILITY RATIOS & MARKET TESTS

University

10 Qs

Training External

Training External

University

15 Qs

PIPING TECHNIQUES

PIPING TECHNIQUES

9th Grade - University

10 Qs

Quizomania-2024 Round 1

Quizomania-2024 Round 1

University

15 Qs

MCQ_VLSI

MCQ_VLSI

Assessment

Quiz

Other

University

Medium

Created by

KALIESWARI.C AP/ECE

Used 3+ times

FREE Resource

AI

Enhance your content in a minute

Add similar questions
Adjust reading levels
Convert to real-world scenario
Translate activity
More...

10 questions

Show all answers

1.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

In accordance to the scaling technology, the total delay of the logic circuit depends on ______

a. The capacitor to be charged

b. The voltage through which capacitance must be charged

c. Available current

d. All of the above

2.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

In high noise margin (NMH), the difference in magnitude between the maximum HIGH output voltage of driving gate and the maximum HIGH voltage is recognized by the _________gate.

a. Driven

b. Receiving

c. Both a and b

d. None of the above

3.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which factor/s play/s a crucial role in determining the speed of CMOS logic gate?

a. Load capacitance

b. Supply voltage

c. Gain factor of MOS

d. All of the above

4.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

In CMOS circuits, which type of power dissipation occurs due to switching of transient current and charging & discharging of load capacitance?

a. Static dissipation

b. Dynamic dissipation

c. Both a and b

d. None of the above

5.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

For complex gate design in CMOS, OR function needs to be implemented by _______ connection/s of MOS.

a. Series

b. Parallel

c. Both series and parallel

d. None of the above

6.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

In pull-up network, PMOS transistors of CMOS are connected in parallel with the provision of conducting path between output node & Vdd yielding _____ output.

a. 1

b. 0

c. Both a and b

d. None of the above

7.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

In CMOS inverter, the propagation delay of a gate is the/an _________ transition delay time for the signal during propagation from input to output especially when the signal changes its value.

a. Highest

b. Average

c. Lowest

d. None of the above

Access all questions and much more by creating a free account

Create resources

Host any resource

Get auto-graded reports

Google

Continue with Google

Email

Continue with Email

Classlink

Continue with Classlink

Clever

Continue with Clever

or continue with

Microsoft

Microsoft

Apple

Apple

Others

Others

Already have an account?