
MCQ_VLSI
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KALIESWARI.C AP/ECE
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10 questions
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1.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
In accordance to the scaling technology, the total delay of the logic circuit depends on ______
a. The capacitor to be charged
b. The voltage through which capacitance must be charged
c. Available current
d. All of the above
2.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
In high noise margin (NMH), the difference in magnitude between the maximum HIGH output voltage of driving gate and the maximum HIGH voltage is recognized by the _________gate.
a. Driven
b. Receiving
c. Both a and b
d. None of the above
3.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
Which factor/s play/s a crucial role in determining the speed of CMOS logic gate?
a. Load capacitance
b. Supply voltage
c. Gain factor of MOS
d. All of the above
4.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
In CMOS circuits, which type of power dissipation occurs due to switching of transient current and charging & discharging of load capacitance?
a. Static dissipation
b. Dynamic dissipation
c. Both a and b
d. None of the above
5.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
For complex gate design in CMOS, OR function needs to be implemented by _______ connection/s of MOS.
a. Series
b. Parallel
c. Both series and parallel
d. None of the above
6.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
In pull-up network, PMOS transistors of CMOS are connected in parallel with the provision of conducting path between output node & Vdd yielding _____ output.
a. 1
b. 0
c. Both a and b
d. None of the above
7.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
In CMOS inverter, the propagation delay of a gate is the/an _________ transition delay time for the signal during propagation from input to output especially when the signal changes its value.
a. Highest
b. Average
c. Lowest
d. None of the above
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