Verilog Fundamentals

initial statement is

• Synthesizable

• Not Synthesizable

always construct is Synthesizable

• True

• False

#5 is Synthesizable

• True

• False

= and <= represent

• Non-blocking and Blocking Assingment respectively

• Blocking and Non-blocking Assingment respectively

Verilog is an

• Case Insensitive

• Case Sensitive

• Can't say

Integer datatype is allocated ______ number of bits

• 16

• 32

• 64

• 8

reg [4:1] pwm will initialize variable of _______ bits

• 3

• 4

• 5

• 6

{,} is used to perform which operation

• concat

• Division

• Exponent

• Mod

The most appropriate modeling style to implement Traffic light controller will be

• Dataflow

• Structural

• Behavioral

• Switch

{1'b0, 2'b01, 3'b0} will result in

• 6'b 001001

• 6'b 001000

• 4'b 0010

• 4'b 0100