Digital Design Quiz - Round 2

The given code represents a/an

• Synchronous high reset

• Asynchronous low reset

• Synchronous low reset

• Asynchronous high reset

• Which statement/statements are correct about flip-flops and latches in design considerations?​

• In general, a flip-flop will consume more power than that of a latch.

• For similar features, a flip-flop will take lesser area than that of a latch.

• Clock boundaries are rigid for both flip-flops and latches

• None of the above are correct

Which statement/statements are incorrect about a S-R flip-flop?

• Considering a positive edge-triggered S-R flip-flop, the output reflects the input condition when the clock pulse is high

• Binary storage register is one example of the use of S-R flip-flop

• S-R flip-flops can be used to create a transition pulse generator

• In a S-R flip-flop, the output is said to be set when Q=0

Which of the following is not correct about struct literal?

• • Nested braces are used to denote a struct.​

• • structs can use a name with a value or use a data type and default value

• A struct should have a type and type can only be defined using a prefix

• None of the above 

• Assume that the initial state of Q1Q2=1x, what would be the state after 4 pulses?​

• X1

• 01

• 10

• Answer is missing

A design engineer implemented a simpler decoder and encoder using parameterized tasks and functions in SystemVerilog. Please understand the below code segment and identify the correct simulation output he will get.

• • ​

  • Encoder input = 01000000 Encoder output = 010​

  • Decoder input = 11 Decoder output = 1000

• • Encoder input = 01000000 Encoder output = 110​

  • Decoder input = 11 Decoder output = 1000

• • Encoder input = 01000000 Encoder output = 11​

  • Decoder input = 11 Decoder output = 01000000

• • ​

  • Encoder input = 01000000 Encoder output = 110​

  • Decoder input = 110 Decoder output = 01000000

• Which of the following statement/staements are correct about a comparison between VHDL and Verilog (Select all that applies)? ​

• • Packages are used for data type and subprograms declaration in Verilog, where as VHDL does not allow package definitions. ​

• VHDL and Verilog both have compiler directives.

• • VHDL allows using user defined datatypes, where as Verilog does not allow users to define their own data type. ​

• • Packages are used for data type and subprograms declaration in Verilog, where as VHDL does not allow package definitions. ​

Which of the following is equivalent to 11010010000001011100111000.1001001001100011 in binary

• • 3481738.9263 in octal​

• • 55056184.5718131201171875 in decimal​

• • 44A17B8.8267 in hexadecimal​

• None of the above

Which of the following statements are correct about SystemVerilog constraints?

• Use of 4 state values are illegal inside constraints 

• Except implication operator, all other operators are treated bidirectionally in constraints 

• A constraint solver can fail when problem is over-constrained and there is no combination of random values that satisfy the constraints.

• Any SystemVerilog expression which includes variables and constants of integral type can be used inside constraints. 

Which of the following is a function of a multiplexer? 

• It amplifies information

• It boosts information

• It removes noise

• Both a & b