Communication Lab Viva_S6_ECA

In Delta Modulation, the slope overload distortion error can be minimized by:

• Decreasing the step size

• keeping the step size constant

• keeping the step size zero

• increasing the step size

A Delta modulation system input applied 10kHz, 1 Vpp. The signal is sampled 10 times more than the Nyquist rate. What is the minimum step size required to prevent slope overload?

• 0.157 V

• 1.57 V

• 15.7 V

• .0157 V

CD 4016 is a

• CMOS IC with 6 analog switches

• NMOS IC with 6 analog switches

• CMOS IC with 4 analog switches

• NMOS IC with 4 analog switches

Given the pin diagram of CD 4016 in one of the options for your reference. Using this, Identify the circuit given:

• 
• BPSK

• BASK

• BFSK

Calculate the centre frequency (approximate) of the VCO output in the circuit diagram given

• 66 kHz

• 6.6 kHz

• 666 kHz

• 666 Hz

Demodulation of a delta modulated signal can be achieved by:

• differentiation

• sampling

• Integration

• Bandpass filtering

In PLL, the capture range is always _______ than the lock range.

• lesser

• greater

• equal to

The Logic gate that works similar to phase detector in a PLL circuit is:

• AND Gate

• OR Gate

• XOR gate

• NOR Gate

The total time taken by the PLL to establish lock is called

• pull-in time

• pull-out time

• tracking time

• locking time

For a BPSK modulator with a carrier frequency of 70 MHz and input bit rate of 10 Mbps, the maximum Upper Side Frequency (USF) and minimum Lower Side Frequency (LSF) are respectively

• 85 MHz and 65 MHz

• 75 MHz and 65 MHz

• 55 MHz and 45 MHz

• 75 MHz and 45 MHz