Quiz 2 Review

At state S1 = 0, S0 = 1, B = 1, what is N1, N0, and OUT?

• 1, 0, 1

• 0, 1, 1

• 1, 1, 1

• 0, 0, 0

What are the most efficient kmap groupings?

• AB + BC

• C

• BC

• A’BC

What are the most efficient kmap groupings?

• B’C + AB’ + AC + A’BC’

• ABC + BC + C

• AC + A’B + BC

• BC’ + A’B + A’C’ + AB’C

Which of the following statements correctly distinguishes combinational logic from sequential logic?

• Combinational logic circuits use memory elements to store past inputs, while sequential logic circuits do not

• The output of a combinational logic circuit depends only on the current inputs, while the output of a sequential logic circuit depends on both current and past state.

• Sequential logic circuits are faster than combinational logic circuits because they do not use feedback paths

• Both combinational and sequential logic circuits produce the same output for a given set of inputs regardless of previous states.

Which of the following circuits uses sequential logic?

• 
• 
• 
• 

Which statement correctly describes the difference between edge-triggered and level-triggered circuits and their associated components?

• Edge-triggered circuits respond continuously while the clock signal is HIGH, while level-triggered circuits respond only at a clock transition.

• Edge-triggered circuits change output only during a rising or falling clock edge, while level-triggered circuits respond as long as the clock signal remains at a specific level.

• Both edge-triggered and level-triggered circuits respond continuously to input changes regardless of the clock signal.

• Edge-triggered circuits are used only in combinational logic, while level-triggered circuits are used in sequential logic.

An RS-Latch has a current output of Q = 0. If the inputs are S = 1 and R = 0, what will be the next output?

• 0

• 1

• Undefined

• It will toggle forever

What is the output of this clock diagram of a Gated D-Latch at the first vertical line?

• 1

• 0

What is the output of this clock diagram of a Rising Edge D Flip-Flop at the third vertical line?

• 1

• 0

What is the addressability of a system that has 256 memory locations, and each memory location stores 8 bits?

• 8

• 256

• 11

• 12