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VLSI Design Quiz updated on 20092020

Total questions: 81

Worksheet time: 43mins

Name
Class
Date
1.
Which truth table is this?
a)
XOR
b)
NAND
c)
NOR
d)
NOT
2.
Which truth table is this?
a)
NAND
b)
AND
c)
OR
d)
NOR
3.

The output of an exclusive-NOR gate is 1,Which input combination is correct?

a)

A = 1 B = 0

b)

A = 0 B = 1

c)

A = 0 B = 0

d)

none of the above

4.
A transistor can act as a ___________. 
a)
resistor
b)
battery
c)
switch
d)
power source
5.

VLSI technology uses ________ to form integrated circuit

a)

transistors

b)

switches

c)

diodes

d)

buffers

6.

The CMOS gate circuit of NOT gate is

a)
b)
c)
d)
7.

The CMOS logic circuit for NAND gate is

a)
b)
c)
d)

None of the mentioned

8.

The CMOS logic circuit for NOR gate is

a)
b)
c)
d)
9.

VLSI stands for

a)

Very limited scale integration

b)

Very large scale integration

c)

very long scale integration

d)

none of these

10.

CMOS technology is used in developing

a)

microprocessors

b)

microcontrollers

c)

digital logic circuits

d)

all of the mentioned

11.

How many terminals are there for a MOSFET

a)

Two

b)

Three

c)

Four

d)

Five

12.

Small scale Integration circuits have

a)

10 to 100 Transistors

b)

100 to 1000 Transistors

c)

1000 to 20000 Transistors

d)

20000 to 1Million Transistors

13.

In MOS transistors, _____ is used for their gate

a)

Metal

b)

Silicon di Oxide

c)

Source/Drain

d)

Polysilicon

14.

All circuit components and interconnections are formed on single thin ___________(substrate) is called monolithic IC

a)

wafer

b)

sand

c)

glass

d)

non of them

15.

The first step of IC Manufacturing is _________________

a)

Masking

b)

wafer production

c)

Etching

d)

None of them

16.

The wafer is a round slice of ______________material such as silicon

a)

Semiconductor

b)

Insulator

c)

Conductor

d)

None of them

17.

_________MOSFET is also called as dual MOSFET

a)

depletion

b)

enhancement

c)

JFET

d)

BJT

18.

Transistors rely on ________, materials that are neither pure insulators nor pure conductors.

a)

semiconductors

b)

semi-insulators

c)

diodes

d)

integrated circuits

19.

Medium scale Integration circuits have

a)

10 to 100 Transistors

b)

100 to 1000 Transistors

c)

1000 to 20000 Transistors

d)

20000 to 1Million Transistors

20.

Large scale Integration circuits have

a)

10 to 100 Transistors

b)

100 to 1000 Transistors

c)

1000 to 20000 Transistors

d)

20000 to 1Million Transistors

21.

Very Large scale Integration circuits have

a)

10 to 100 Transistors

b)

100 to 1000 Transistors

c)

1000 to 20000 Transistors

d)

20000 to 1Million Transistors

22.
Which truth table is this?
a)
XOR
b)
NAND
c)
NOR
d)
NOT
23.
Which truth table is this?
a)
NAND
b)
AND
c)
OR
d)
NOR
24.

NMOS has N-substrate

a)

TRUE

b)

FALSE

25.

PMOS has P-substrate

a)

TRUE

b)

FALSE

26.

nMOS devices are formed in

a)

p-type substrate of high doping level

b)

n-type substrate of low doping level

c)

p-type substrate of moderate doping level

d)

n-type substrate of high doping level

27.

Source and drain in nMOS device are isolated by

a)

a single diode

b)

two diodes

c)

three diodes

d)

four diodes

28.

MOS transistors consists of

a)

semiconductor layer

b)

metal layer

c)

layer of silicon dioxide

d)

all of the mentioned

29.

In CMOS fabrication, nMOS and pMOS are integrated in same substrate.

a)

true

b)

false

30.

P-well is created on

a)

p subtrate

b)

n substrate

c)

p & n substrate

d)

none of the mentioned

31.

The n-type semiconductor have _______ as majority carriers

a)

Holes

b)

Ions

c)

electrons

d)

positive ions

32.

The oxide layer formed in the MOSFET is

a)

Oxides of Non metals

b)

Poly Silicon oxide

c)

Silicon dioxide

d)

Metal oxide

33.

Which of the following terminals does not belong to the MOSFET?

a)

Drain

b)

Gate

c)

Base

d)

Source

34.

A MOSFET has …………… terminals

a)

4

b)

3

c)

5

d)

2

35.

__________ network to connect the output of 1

a)

pMOS pull up

b)

CMOS

c)

nMOS pull down

d)

all the above

36.

when gate is ___________ nMOS transistor is ON

a)

low

b)

high

c)

high impendence

d)

low or high

37.

In MOS structure for the condition Vg > Vt it will in ___________

a)

inversion region

b)

accumulation region

c)

depletion region

d)

all the above

38.

nMOS transistor the Ids value is '0' for ______________

a)

linear region

b)

cutoff region

c)

saturation region

d)

unsaturated region

39.

The photoresist layer is exposed to ____________


a)

a) Visible light

b)

b) Ultraviolet light

c)

c) Infra red light

d)

d) LED

40.

The electrical equivalent component for MOS structure is:

a)

a) Resistor

b)

b) Capacitor

c)

c) Inductor

d)

d) Switch

41.

Ids depends on ___________

a)

a) Vg

b)

b) Vds

c)

c) Vdd

d)

d) Vss

42.

In CMOS logic circuit the n-MOS transistor acts as

a)

Load

b)

Pull up network

c)

Pull down network

43.

In CMOS logic circuit the p-MOS transistor acts as

a)

Load

b)

Pull up network

c)

Pull down network

d)

Short to ground

44.

In CMOS logic circuit, the switching operation occurs because

a)

Both n-MOSFET and p-MOSFET turns OFF simultaneously for input ‘0’ and turns ON simultaneously for input ‘1’

b)

Both n-MOSFET and p-MOSFET turns ON simultaneously for input ‘0’ and turns OFF simultaneously for input ‘1’

c)

N-MOSFET transistor turns ON, and p-MOSFET transistor turns OFF for input ‘1’ and N-MOS transistor turns OFF, and p-MOS transistor turns ON for input ‘0’

d)

None of the mentioned

45.

In enhancement MOSFET, the magnitude of output current __________ due to an increase in the magnitude of gate potentials.

a)

a. Increases

b)

b. Remains constant

c)

c. Decreases

d)

d. None of the above

46.

Which type of MOSFET exhibits no current at zero gate voltage?

a)

a. Depletion MOSFET

b)

b. Enhancement MOSFET

c)

c. Both a and b

d)

d. None of the above

47.

In MOS transistors, _____ is used for their gate

a)

Metal

b)

Silicon di Oxide

c)

Source/Drain

d)

Polysilicon

48.

The n-MOS transistor is made up of

a)

N-type source, n-type drain and p-type Substrate

b)

N-type source, p-type drain and p-type Substrate

c)

P-type source, n-type drain and n-type Substrate

d)

P- type source, p-type drain and n-type Substrate

49.

All circuit components and interconnections are formed on single thin ___________(substrate) is called monolithic IC

a)

wafer

b)

sand

c)

glass

d)

non of them

50.

The first step of IC Manufacturing is _________________

a)

Masking

b)

wafer production

c)

Etching

d)

None of them

51.

__________voltage is to be given to the gate of enhancement MOSFET to form channel and start to conduct.

a)

Positive

b)

Negative

c)

any

d)

both

52.

The p-MOS transistor is made up of

a)

N-type source, n-type drain and p-type Substrate

b)

N-type source, p-type drain and p-type Substrate

c)

P-type source, n-type drain and n-type Substrate

d)

P- type source, p-type drain and n-type Substrate

53.

Which among the following MOSFET type will be in ON condition when VGS = -ve volt

a)

N - Channel Depletion

b)

N - Channel Enhancement

c)

P- Channel Depletion

54.

Which among the following MOSFET type will be in ON condition when VGS = 0 volt

a)

N-Channel Depletion

b)

N-Channel Enhancement

c)

P-Channel Enhancement

55.

Which among the following MOSFET type will be in ON condition when VGS = +ve volt

a)

N-Channel Enhancement

b)

P-Channel Enhancement

c)

P-Channel Depletion

56.

Match the given transfer characteristics with the below symbol.

a)
b)
c)
d)
57.

NMOS has N-substrate

a)

TRUE

b)

FALSE

58.

PMOS has P-substrate

a)

TRUE

b)

FALSE

59.

nMOS devices are formed in

a)

p-type substrate of high doping level

b)

n-type substrate of low doping level

c)

p-type substrate of moderate doping level

d)

n-type substrate of high doping level

60.

In depletion mode, source and drain are connected by

a)

insulating channel

b)

conducting channel

c)

Vdd

d)

Vss

61.

In enhancement mode, device is in _________ condition

a)

conducting

b)

non conducting

c)

partially conducting

d)

insulating

62.

Enhancement mode device acts as ____ switch, depletion mode acts as _____ switch

a)

open, closed

b)

closed, open

c)

open, open

d)

close, close

63.

______ architecture is used to design VLSI

a)

system on a device

b)

single open circuit

c)

system on a chip

d)

system on a circuit

64.

The design flow of VLSI system is

1. Architecture design 2. Fabrication 3. System Specification 4. Circuit Design 5. Packaging and Testing 6. logic design 7. Physical Design 8. Functional Design

a)

3-1-8-6-4-7-2-5

b)

3-2-8-6-4-7-1-5

c)

3-1-5-6-4-7-2-8

d)

7-1-8-6-4-3-2-5

65.

Electrical charge flows from

a)

source to drain

b)

drain to source

c)

source to ground

d)

source to gate

66.

MOSFET has greatest application in digital circuit due to

a)

Low power consumption

b)

Less noise

c)

Small amount of space it takes on a chip

d)

All of the above

67.

Ids depends on

a)

Vg

b)

Vds

c)

Vdd

d)

Vss

68.

What is Moore's law

a)

Number of transistors increases every 12 months

b)

Number of transistors doubles every 18 months

c)

Number of transistors increases every 12 months

d)

Number of transistors triples every 18 months

69.

An Integrated Circuit (IC) is also called as __________

a)

FPGA

b)

MIcrocontroller

c)

Chip or Microchip

d)

None of them

70.

IC can function as _________ etc.

a)

timer, counter

b)

oscillator

c)

amplifier

d)

computer memory

e)

All of them

71.

Inverters are essential for ________

a)

NAND gates

b)

NOR gates

c)

sequential circuits

d)

all of the mentioned

72.

In basic inverter circuit _____________ is connected to ground.

a)

source

b)

gates

c)

drain

d)

resistance

73.

In inverter circuit ________ transistors is used as load

a)

enhancement mode

b)

depletion mode

c)

all of the mentioned

d)

none of the mentioned

74.

In nMOS inverter configuration depletion mode device is called as ________

a)

pull up

b)

pull down

c)

all of the mentioned

d)

none of the mentioned

75.

How is nMOS inverter represented?

a)
b)
c)
d)
76.

Pass transistors are transistors used as ________

a)

switches connected in series

b)

switches connected in parallel

c)

inverters used in series

d)

inverter used in parallel

77.

CMOS inverter has ------- regions of operation

a)

3

b)

4

c)

2

d)

5

78.

In the region where inverter exhibits gain, the two transistors are in ------------ region

a)

saturation

b)

linear

c)

cut-off

d)

non saturation

79.

If βn = βp, then Vin is equal to

a)

Vdd

b)

Vss

c)

2Vdd

d)

0.5Vdd

80.

How many transistors might bring up latch up effect in p-well structure?

a)

2

b)

3

c)

1

d)

4

81.

Substrate doping level should be decreased to avoid the latch-up effect.

a)

true

b)

false

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