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WorksheetsFundamentals of IC Testing 1
Total questions: 20
Worksheet time: 11mins
What is VIL test?
to test the voltage of the output pins at logic high
to test the voltage of the output pins at logic low
to test the voltage of the input pins at logic low
to test the voltage of the input pins at logic high
Why edge strobe is not a perfect test?
it is only works for signal with low noise
it is a faster method of strobing
it is only one point of strobe
noise cud come out of window
Mary searched two ICs on the VOL, IC1 measured 0.79V, and IC2 measured 0.81V. Which one is correct?
IC1 and IC2 can be used
IC2 can be used but IC1 need to be scrapped
both of the ICs need to be scrapped
Mary shud keep IC1
Sam did a search on two ICs, IC1 has VOH 2.42V and IC2 has VOH 2.401V. Which one is true
Sam shud keep both of the units
IC1 failed but IC2 passed
IC1 passed but IC2 failed
Sam should change his specs limits
What are patterns?
supply the logic state for a pin
supply the levels test for each of the logics
supply when to strobe and when to compare
all of them
An IC has 300 input pins. How many pattern resources that it needs from a tester?
100
200
300
400
The setup time for a pin is 10ns, how do you measure whether a unit pass or fail?
set setup time at 10ns at tester, check output signal
set setup time at 8ns at tester, check output signal
set setup time at 12ns at tester, check output signal
set setup time at 11ns at tester, check output signal
What is Tp?
Setup time
Hold time
Rise Time
Propagation delay
How do you test setup time for 100 pins?
must use a pattern set.
loop 100 times in different clock cycle
measure manually
it can not be measured
Which one is not true?
it requires 13 CLK cycles to perform a basic functional test
each AND gate is independent
if one of the AND gate is damaged, the rest still can be used
if one of the AND gate is damaged, you can't use the other gates.
Why we do final testing?
to ensure quality is met
as a feedback mechanism
to strenghten the device
act as a burn in mechnism
Why is Ioh reading is negative?
because the direction is out of the DUT
because the direction is to the DUT
because it flows from lower voltage value
because it flows from lower current value
What cause CMOS latch-up?
overvoltage spikes
wrong polarity
the existence parisitic BJT transistor in CMOS circuit
all are correct
What is this diagram?
step to add a load at the ouput pin
step to add an external hardware at the output pin
proper step before sending signal to the handler
steps to prevent from cmos latchup
Pentium II has 273 pins and max settings for the pogo is at 40g per pin. What is the plunger force cpapability require at the handler site?
9 kg
10 kg
11 kg
12 kg
What is Vih test?
A current range that is accepted as the logic 1 at the output pin
A voltage range that is accepted as logic 1 at the output pin
A current range which is accepted as logic 1 at the input pin
A voltage range which is accepted as logic 1 at the input pin
What are the differences between shorts test in Digital IC and Analog IC?
the uses of UPD and LPD
Analog IC need to check the resistance between pins
there is no difference
none is corrrect
Sam looks at the volmeter @V_measure. In normal condition what will be the reading?
0.3 V
-0.7 V
-0.3V
None is correct
Describe the region in blue?
not use in continuity test
when there is no power, it becomes malfuncion
it used a lot of test pattern
it determines the binning
What is IIH test?
is the leakage test for logic low
is the leakage test for logic high
is a leakage test does not matter for logic low or high
none is correct
