WorksheetsLogic Circuit Design Question Bank
Total questions: 254
Worksheet time: 2hrs 7mins
Name
Class
Date
1.
Decimal 43 in Hexadecimal and BCD number system is respectively
a)
B2, 0100 0011
b)
2B, 0100 0011
c)
2B, 0011 0100
d)
B2, 0100 0100
2.
The range of signed decimal numbers that can be represented by 6-bite 1’s complement number is
a)
-31 to +31
b)
-63 to +64
c)
-64 to +63
d)
-32 to +31
3.
Convert (1056)16 to ( ? )8
a)
10136
b)
10126
c)
10125
d)
11126
4.
Convert (11672)8 to ( ? )16
a)
13BA
b)
13CA
c)
12BA
d)
12BC
5.
Convert (1001001100)2 to ( ? )6
a)
3420
b)
2421
c)
2420
d)
2320
6.
Convert base 10 to base 8 : (1032.6875)10
a)
2010.29
b)
2011.45
c)
2010.54
d)
2100.54
7.
Add the following hexadecimal number. 8AB + B78
a)
1423
b)
142A
c)
1B23
d)
1422
8.
If the number of bits in the sum exceeds the number of bits in each added numbers, it results in _________
a)
Successor
b)
Overflow
c)
Underflow
d)
Predecessor
9.
The size of double word is
a)
16 bits
b)
32 bits
c)
8 bits
d)
4 bits
10.
The addition of +19 and +43 results as _________ in 2’s complement system.
a)
101110
b)
1001101
c)
100010
d)
1100101
11.
On subtracting (01010)2 from (11110)2 using 1’s complement, we get ____________
a)
1001
b)
11010
c)
10101
d)
10100
12.
On addition of 28 and 18 using 2’s complement, we get ____________
a)
101110
b)
101110
c)
101111
d)
1001111
13.
How many bits would be required to encode decimal numbers 0 to 9999 in straight binary codes?
a)
14
b)
12
c)
16
d)
32
14.
The advantage of 2’s complement system is that
a)
Different Arithmetic operations are required
b)
No arithmetic operations are required
c)
Two arithmetic operations are required
d)
Only one arithmetic operation is required
15.
On addition of -46 and +28 using 2’s complement, we get
a)
-10010
b)
-101
c)
1011
d)
100101
16.
Convert binary to octal: (110110001010)
a)
(6745
b)
4532
c)
6612
d)
-6745
17.
A three digit decimal number requires ________ for representation in the conventional BCD format.
a)
24 bits
b)
6 bits
c)
8 bits
d)
12 bits
18.
The number of 1's in 8-bit unsigned representation of 127 in its 2's complement
form is m and that in 1's complement form is n. What is the value of m:n
a)
2:1
b)
1:2
c)
3:1
d)
1:3
19.
What is the decimal value of the ASCII code for the letter 'A'?
a)
65
b)
67
c)
69
d)
71
20.
Convert binary number 10110 to gray code
a)
11101
b)
10110
c)
11100
d)
10010
21.
Find the decimal equivalent of XS-3 code 1100 1010 0011.0111 0101
a)
950.62
b)
970.01
c)
950.42
d)
970.42
22.
What is the range of values that can be represented by an n-bit signed fixed-point number?
a)
-(2^(n-1)) to (2^(n-1))-1
b)
-(2^n) to (2^n)-1
c)
0 to (2^n)-1
d)
0 to 2^n
23.
How many bits are required to represent the BCD equivalent of a 3-digit decimal number?
a)
8
b)
12
c)
16
d)
20
24.
Which of the following is true about BCD representation?
a)
It is a self-complementing code.
b)
It is a weighted code.
c)
It is a variable-length code.
d)
It is used only for positive numbers.
25.
What is the BCD representation of the decimal number 99?
a)
10011001
b)
11110011
c)
11000110
d)
10101010
26.
What is the largest positive value that can be represented by a 16-bit signed fixed-point number?
a)
2^7-1
b)
2^15-1
c)
2^31-1
d)
2^63-1
27.
What is the decimal equivalent of the binary fixed-point number 1010.11?
a)
10.75
b)
11.5
c)
9.25
d)
10.25
28.
The number of bytes required to represent the decimal number 1856357 in packed BCD form is
a)
2
b)
4
c)
6
d)
8
29.
Which of the following is an advantage of floating-point numbers over fixed-point numbers?
a)
Fixed-point numbers have higher precision.
b)
Floating-point numbers can represent a wider range of values.
c)
Fixed-point numbers are more efficient for storage.
d)
Floating-point numbers have faster computation speed.
30.
What is the main advantage of Gray code over binary code?
a)
Gray code uses fewer bits to represent the same number.
b)
Gray code is easier to convert to decimal representation.
c)
Gray code has a faster execution time.
d)
Gray code is resistant to errors during transmission.
31.
Which logical operation is commonly used to convert binary code to Gray code?
a)
NOT
b)
AND
c)
NOR
d)
XOR
32.
What is the ASCII code for the space character?
a)
30
b)
32
c)
34
d)
36
33.
Covert 11000110 gray code.
a)
10100101
b)
11001010
c)
10110000
d)
10000111
34.
What is the Hamming distance between any two adjacent codes in Gray code?
a)
0
b)
1
c)
2
d)
It varies depending on the number of bits.
35.
What is the binary representation of the decimal number 7 in Excess-3 code?
a)
1010
b)
1110
c)
1101
d)
None of the above
36.
In Excess-3 code, what is the decimal value represented by the binary number 1011?
a)
1
b)
3
c)
5
d)
8
37.
How many unique characters can be represented by ASCII?
a)
64
b)
128
c)
256
d)
512
38.
What does ASCII stand for?
a)
American Standard Code for International Information
b)
American Standard Code for Information Interchange
c)
Associated Standard Code for International Interchange
d)
Association of Standardized Code for Information Interface
39.
In Verilog, a testbench is used for:
a)
Synthesis of digital circuits
b)
Defining module interfaces
c)
Simulating and verifying the design
d)
Debugging hardware components
40.
Which keyword is used to specify a delay in Verilog?
a)
delay
b)
wait
c)
#
d)
@
41.
The purpose of a clock signal in Verilog is to:
a)
Control the timing of the design
b)
Assign values to registers
c)
Implement combinational logic
d)
Define the size of a module
42.
Which operator is used for concatenation in Verilog?
a)
+'
b)
<<
c)
|
d)
{}
43.
The $display system function in Verilog is used for:
a)
Declaring variables
b)
Defining modules
c)
Printing messages during simulation
d)
Controlling the simulation flow
44.
In Verilog, an array can be declared using which syntax?
a)
array[3:0]
b)
array[0:3]
c)
array[0][3]
d)
array(3:0)
45.
Which keyword is used to specify the size of an input or output port in a module?
a)
size
b)
width
c)
bit
d)
parameter
46.
In Verilog, a parameter is used for:
a)
Specifying the size of a module
b)
Declaring internal variables
c)
Controlling simulation time
d)
Specifying the number of clock cycles
47.
The posedge keyword in Verilog is used to represent:
a)
Falling edge of a clock signal
b)
Rising edge of a clock signal
c)
Level-sensitive behavior
d)
Non-blocking assignment
48.
Which operator is used for logical negation in Verilog?
a)
&
b)
|
c)
~
d)
^
49.
The case statement in Verilog is used for:
a)
Sequential behavior
b)
Combinational behavior
c)
Clock edge sensitivity
d)
Looping constructs
50.
Which Verilog construct is used for iterative behavior?
a)
for loop
b)
if-else statement
c)
case statement
d)
always block
51.
In Verilog, the disable statement is used to:
a)
Stop the simulation
b)
Disable a module instantiation
c)
Disable a procedural block
d)
Halt the execution of the program
52.
Verilog is commonly used in
a)
Web development
b)
Database management
c)
Digital system design
d)
Mobile application development
53.
Verilog supports which modeling styles?
a)
Structural and functional
b)
Behavioral and functional
c)
Structural and behavioral
d)
Functional and gate-level
54.
The assign keyword in Verilog is used for:
a)
Declaring variables
b)
Defining modules
c)
Assigning values to wires
d)
Controlling the simulation flow
55.
In Verilog, the always block is used for:
a)
Declaring variables
b)
Defining modules
c)
Specifying timing delays
d)
Describing sequential behavior
56.
Which keyword is used to define a wire in Verilog?
a)
input
b)
output
c)
wire
d)
reg
57.
In Verilog, blocking assignments (=) are used for:
a)
Concurrent assignments
b)
Sequential assignments
c)
Delayed assignments
d)
Non-blocking assignments
58.
The ternary operator in Verilog is represented by:
a)
&&
b)
==
c)
?:
d)
<=
59.
Which of the following is not a Boolean postulate?
a)
Idempotent Law
b)
Distributive Law
c)
Complement Law
d)
Transitive Law
60.
De Morgan's first theorem states that the complement of a _______ is equal to the _______ of the individual terms.
a)
sum, product
b)
product, sum
c)
sum, sum
d)
product, product
61.
The principle of duality states that any algebraic expression remains unchanged when:
a)
The variables are rearranged in alphabetical order
b)
The expression is simplified using Boolean postulates
c)
All the operators are replaced with their complements
d)
The expression is written in reverse order
62.
Which method is used to simplify Boolean expressions by reducing the number of terms or literals?
a)
Karnaugh Map
b)
Quine-McCluskey method
c)
De Morgan's Theorem
d)
Principle of Duality
63.
What is the result of minimizing the Boolean expression (A + B)(A + C)?
a)
A + B + C
b)
A + BC
c)
A(B + C)
d)
AB + AC
64.
The sum of products (SOP) form of a Boolean expression is obtained by:
a)
Multiplying all the terms together
b)
Adding all the terms together
c)
Taking the complement of each term
d)
Simplifying using De Morgan's Theorem
65.
The product of sums (POS) form of a Boolean expression is obtained by:
a)
Multiplying all the terms together
b)
Adding all the terms together
c)
Taking the complement of each term
d)
Simplifying using De Morgan's Theorem
66.
Which Boolean postulate states that the sum of a variable and its complement is always equal to the universal set?
a)
Complement Law
b)
Idempotent Law
c)
Universal Law
d)
Distributive Law
67.
De Morgan's second theorem states that the complement of a _______ is equal to the _______ of the individual terms.
a)
sum, product
b)
product, sum
c)
sum, sum
d)
product, product
68.
The principle of duality can be applied to Boolean expressions with how many variables?
a)
Only one variable
b)
Two variables
c)
Any number of variables
d)
Three or more variables
69.
Which method is used to minimize Boolean expressions by combining adjacent terms and eliminating redundant variables?
a)
Quine-McCluskey method
b)
Karnaugh Map
c)
De Morgan's Theorem
d)
Principle of Duality
70.
What is the result of minimizing the Boolean expression (A + B)(A' + C)?
a)
A' + B' + C'
b)
A' + BC
c)
A(B' + C)
d)
AB' + AC
71.
The sum of products (SOP) form of a Boolean expression consists of:
a)
Multiple terms added together, where each term is a product of literals
b)
Multiple terms multiplied together, where each term is a sum of literals
c)
A single term, which is a sum of literals
d)
A single term, which is a product of literals
72.
The product of sums (POS) form of a Boolean expression consists of:
a)
Multiple terms added together, where each term is a product of literals
b)
Multiple terms multiplied together, where each term is a sum of literals
c)
A single term, which is a sum of literals
d)
A single term, which is a product of literals
73.
Which Boolean postulate states that the sum of a variable and its complement is always equal to 1?
a)
Complement Law
b)
Idempotent Law
c)
Universal Law
d)
Distributive Law
74.
De Morgan's theorem can be used to convert a product of sums expression into a:
a)
Sum of products expression
b)
Sum of differences expression
c)
Product of sums expression
d)
Product of differences expression
75.
The principle of duality states that if an algebraic expression is true for a given set of inputs, then its dual expression is true for:
a)
The same set of inputs
b)
The complement set of inputs
c)
The inverse set of inputs
d)
The universal set of inputs
76.
Which method is used to minimize Boolean expressions by grouping adjacent terms that differ by only one variable?
a)
Quine-McCluskey method
b)
Karnaugh Map
c)
De Morgan's Theorem
d)
Consensus theorem
77.
What is the result of minimizing the Boolean expression A + A'BC + AB' + A'B + BC'?
a)
A + B + C
b)
A + B'C'
c)
AB' + A'C + BC'
d)
A'B'C'
78.
The sum of products (SOP) form of a Boolean expression can be represented as:
a)
A single term, which is a sum of literals
b)
Multiple terms added together, where each term is a product of literals
c)
A single term, which is a product of literals
d)
Multiple terms multiplied together, where each term is a sum of literals
79.
The product of sums (POS) form of a Boolean expression can be represented as:
a)
A single term, which is a sum of literals
b)
Multiple terms added together, where each term is a product of literals
c)
A single term, which is a product of literals
d)
Multiple terms multiplied together, where each term is a sum of literals
80.
The expression for Absorption law is given by _________
a)
A + AB = A
b)
A + AB = B
c)
AB + AA’ = A
d)
A + B = B + A
81.
Complement of the expression A’B + CD’ is _________
a)
(A’ + B)(C’ + D)
b)
(A + B’)(C’ + D)
c)
(A’ + B)(C’ + D)
d)
(A + B’)(C + D’)
82.
The Boolean function A + BC is a reduced form of ____________
a)
AB + BC
b)
(A + B)(A + C)
c)
A’B + AB’C
d)
(A + C)
83.
A product term containing all K variables of the function in either complemented or uncomplemented form is called a __________
a)
Minterm
b)
Maxterm
c)
Midterm
d)
∑ term
84.
A variable on its own or in its complemented form is known as a __________
a)
Product Term
b)
Literal
c)
Sum Term
d)
Word
85.
Maxterm is the sum of __________ of the corresponding Minterm with its literal complemented.
a)
Terms
b)
Words
c)
Numbers
d)
Nibble
86.
There are _____________ Minterms for 3 variables (a, b, c).
a)
0
b)
2
c)
8
d)
1
87.
The expression Y=AB+BC+AC shows the _________ operation.
a)
EX-OR
b)
SOP
c)
NOR
d)
POS
88.
In Boolean algebra, the OR operation is performed by which properties?
a)
Associative properties
b)
Commutative properties
c)
Distributive properties
d)
All of the Mentioned
89.
The canonical form of a Boolean expression is also known as:
a)
Standard form
b)
Normal form
c)
Canonical form
d)
Simplified form
90.
In Boolean algebra, the canonical form consists of:
a)
Sum of Products (SOP) and Product of Sums (POS)
b)
Sum of Products (SOP) only
c)
Product of Sums (POS) only
d)
None of the above
91.
Which of the following is an example of a Sum of Products (SOP) canonical form?
a)
(A + B) . (C + D)
b)
(A . B) + (C . D)
c)
(A + B + C + D)
d)
(A . B . C . D)
92.
The Product of Sums (POS) canonical form is obtained by:
a)
Multiplying the variables in a Boolean expression
b)
Adding the variables in a Boolean expression
c)
Adding the minterms that produce a 0 output in a truth table
d)
Adding the maxterms that produce a 1 output in a truth table
93.
The canonical form of a Boolean expression provides a systematic method to:
a)
Simplify the expression using basic logic gates
b)
Implement the expression using universal logic gates
c)
Convert the expression into a circuit diagram
d)
Minimize the number of variables in the expression
94.
A Karnaugh map is a graphical representation of:
a)
Truth table
b)
Logic gates
c)
Boolean expression
d)
Logic circuit diagram
95.
Karnaugh maps are used for:
a)
Minimizing Boolean expressions
b)
Maximizing Boolean expressions
c)
Simplifying logic gates
d)
Designing sequential circuits
96.
How many variables can a Karnaugh map accommodate?
a)
2 variables
b)
3 variables
c)
4 variables
d)
Any number of variables
97.
The entries in a Karnaugh map represent:
a)
Minterms
b)
Maxterms
c)
Variables
d)
Logic gates
98.
Which of the following is a valid grouping rule for Karnaugh map minimization?
a)
Adjacency
b)
Commutativity
c)
Associativity
d)
Distributivity
99.
When minimizing a Boolean expression using a Karnaugh map, each group should contain:
a)
Only 1s
b)
Only 0s
c)
Both 1s and 0s
d)
None of the above
100.
The number of cells in a Karnaugh map group should be a power of:
a)
2
b)
3
c)
4
d)
10
101.
Prime implicants in Karnaugh map minimization represent:
a)
Essential minterms
b)
Essential maxterms
c)
Don't-care conditions
d)
Output variables
102.
In Karnaugh map minimization, don't-care conditions are denoted by:
a)
X
b)
0
c)
1
d)
D
103.
The final minimized Boolean expression obtained from a Karnaugh map represents:
a)
The simplest form of the original expression
b)
The original expression without any changes
c)
The largest possible form of the original expression
d)
The expression with the most variables
104.
Verilog is a hardware description language (HDL) used for:
a)
Designing software applications
b)
Writing operating systems
c)
Modeling digital circuits
d)
Debugging network protocols
105.
Which of the following describes the purpose of module declaration in Verilog?
a)
Defining the inputs and outputs of a module
b)
Specifying the internal logic of a module
c)
Assigning values to variables within a module
d)
Controlling the timing of signals within a module
106.
In Verilog, a wire declaration is used for:
a)
Representing combinational logic
b)
Representing sequential logic
c)
Connecting different modules together
d)
Storing data within a module
107.
The "always" block in Verilog is used for:
a)
Continuous assignment of values to variables
b)
Specifying the order of execution within a module
c)
Modeling sequential behavior using procedural statements
d)
Defining the interface of a module
108.
Which Verilog construct is used to describe combinational logic?
a)
Always block
b)
Initial block
c)
Case statement
d)
Continuous assignment
109.
In Verilog, the "posedge" keyword is used to detect:
a)
Rising edge of a clock signal
b)
Falling edge of a clock signal
c)
Synchronous reset condition
d)
Asynchronous reset condition
110.
What does the "reg" keyword signify in Verilog?
a)
A register variable that stores data within a module
b)
A sequential logic element
c)
A wire connection between modules
d)
An output port of a module
111.
Which Verilog construct is used to describe sequential logic?
a)
Always block
b)
Initial block
c)
Case statement
d)
Continuous assignment
112.
The "#" symbol in Verilog represents:
a)
Bitwise AND operation
b)
Bitwise OR operation
c)
Delay value for simulation
d)
Comment indicato
113.
Which Verilog code snippet correctly implements an AND gate?
a)
assign out = a & b;
b)
assign out = a | b;
c)
assign out = a ^ b;
d)
assign out = ~a;
114.
Which Verilog code snippet correctly implements an NAND gate?
a)
assign out = a & b;
b)
assign out = a | b;
c)
assign out = a ^ b;
d)
assign out = ~(a & b);
115.
Which of the following is the primary function of a comparator in a logic design circuit?
a)
Amplification
b)
Voltage regulation
c)
Comparison
d)
Signal conditioning
116.
Which logic gate is commonly used in the design of comparators?
a)
AND gate
b)
OR gate
c)
NOT gate
d)
XOR gate
117.
Which component is commonly used as a basic building block for designing comparators?
a)
Transistor
b)
Capacitor
c)
Inductor
d)
Resistor
118.
How many control lines are required to select one out of 16 inputs in a multiplexer?
a)
2
b)
3
c)
4
d)
16
119.
In a multiplexer, which of the following is used to select the desired input?
a)
AND gate
b)
OR gate
c)
NOT gate
d)
Select lines
120.
A 4-to-1 multiplexer has:
a)
2 select lines and 4 data inputs
b)
4 select lines and 2 data inputs
c)
1 select line and 4 data inputs
d)
1 select line and 2 data inputs
121.
A 2-to-1 multiplexer has select lines S and data inputs
D0 and D1. If S=0, which of the following represents the output of the multiplexer?
a)
D0
b)
D1
c)
D0 + D1
d)
D0 · D1
122.
What is the primary function of a demultiplexer in a logic design circuit?
a)
Logic inversion
b)
Signal amplification
c)
Data selection
d)
Data distribution
123.
A 1-to-8 demultiplexer has:
a)
3 select lines and 1 data input
b)
8 select lines and 1 data input
c)
1 select line and 8 data outputs
d)
1 select line and 1 data input
124.
In a demultiplexer, which of the following is used to select the desired output?
a)
AND gate
b)
OR gate
c)
NOT gate
d)
Select lines
125.
In an encoder, which of the following represents the number of input lines?
a)
2^N
b)
N^2
c)
N!
d)
N
126.
A 4-to-2 encoder has 4 input lines and 2 output lines.
How many different input combinations can this encoder represent?
a)
4
b)
8
c)
16
d)
2
127.
In a priority encoder, when multiple inputs are
active simultaneously, which input gets the highest priority?
a)
The input with the highest index
b)
The input with the lowest index
c)
The input with the highest voltage level
d)
The input with the lowest voltage level
128.
What is the primary function of an encoder in a logic design circuit?
a)
Logic inversion
b)
Signal amplification
c)
Data compression
d)
Data selection
129.
In a decoder, the number of output lines is determined by:
a)
The number of select lines
b)
The number of input lines
c)
The type of logic gate used
d)
The power supply voltage
130.
How many input lines are required to design a 4-to-16 decoder?
a)
2
b)
4
c)
16
d)
256
131.
A decoder circuit takes a binary input and produces:
a)
Multiple output lines
b)
One output line
c)
No output lines
d)
Random output lines
132.
In a half adder, the output bit S represents:
a)
The sum of the two input bits
b)
The carry generated by the
addition of the input bits
c)
The difference between
the input bits
d)
The exclusive OR (XOR) of the input bits
133.
How many XOR gates are used in a full adder circuit?
a)
1
b)
2
c)
3
d)
4
134.
What is the primary function of a full adder in a logic design circuit?
a)
Addition of two bits
b)
Subtraction of two bits
c)
Multiplication of two bits
d)
Division of two bits
135.
How many XOR gates are used in a full subtractor circuit?
a)
1
b)
2
c)
3
d)
4
136.
A full subtractor circuit takes:
a)
Two input bits and produces a difference bit and a borrow bit
b)
Two input bits and produces
a sum bit and a carry bit
c)
Three input bits and produces
a difference bit and a borrow bit
d)
Three input bits and produces
a sum bit and a carry bit
137.
What is the primary function of a subtractor in a logic design circuit?
a)
Addition of two numbers
b)
Subtraction of two numbers
c)
Multiplication of two numbers
d)
Division of two numbers
138.
What is the purpose of a borrow bit in a subtractor circuit?
a)
It represents the difference between the input bits
b)
It indicates whether a borrow is required during subtraction
c)
It carries the sum bit from one subtractor to the next
d)
It provides overflow detection during subtraction
139.
How many inputs are required to load data in parallel into an 8-bit shift register?
a)
8 inputs
b)
8 inputs
c)
4 inputs
d)
16 inputs
140.
What is the purpose of the parallel load operation in a shift register?
a)
To shift the data through the stages
b)
To load data into multiple stages simultaneously
c)
To reset the shift register to its initial state
d)
To enable the clock signal for shifting
141.
Which input control signal is used to enable the parallel load operation in a shift register?
a)
Clock
b)
Clear
c)
Load
d)
Shift
142.
How many clock cycles are required to shift an 8-bit data pattern through an 8-bit shift register?
a)
1 clock cycle
b)
8 clock cycles
c)
16 clock cycles
d)
It depends on the clock frequency
143.
Which of the following counters has a circular arrangement of flip-flops?
a)
Ring counter
b)
Johnson counter
c)
Ripple counter
d)
Binary counter
144.
What is the purpose of a feedback connection in a ring counter?
a)
To reset the counter
b)
To enable counting
c)
To synchronize the flip-flops
d)
To propagate the clock signal
145.
How many unique states can be represented by an n-bit ring counter?
a)
n
b)
2^n
c)
2^(n-1)
d)
2^(n+1)
146.
How many flip-flops are required to implement an n-bit Johnson counter?
a)
n-1
b)
n
c)
2n
d)
2^n
147.
Which counter is more suitable for applications requiring a non-sequential counting sequence?
a)
Ring counter
b)
Johnson counter
c)
Synchronous counter
d)
Asynchronous counter
148.
Which of the following statements is true regarding an asynchronous counter?
a)
It uses external clock pulses to drive its operation.
b)
It requires a common clock signal for all flip-flops.
c)
It requires a common clock signal for all flip-flops.
d)
It is also known as a ripple counter.
149.
Which of the following is a basic building block of digital circuits?
a)
Transistor
b)
Flip flop
c)
Capacitor
d)
Resistor
150.
Which type of flip flop is constructed using NAND gates?
a)
S-R flip flop
b)
D flip flop
c)
J-K flip flop
d)
T flip flop
151.
The Master-Slave J-K flip flop is made up of how many J-K flip flops?
a)
1
b)
2
c)
4
d)
8
152.
Which type of flip flop is triggered by the edge of a clock signal?
a)
S-R flip flop
b)
D flip flop
c)
J-K flip flop
d)
T flip flop
153.
In an asynchronous counter, the flip-flops are connected in:
a)
Ripple fashion
b)
Master-slave fashion
c)
D-type fashion
d)
JK flip-flop fashion
154.
In a synchronous counter, the flip-flops change states:
a)
On each clock pulse
b)
One at a time, in a sequential manner
c)
In a random fashion
d)
Only when the enable signal is asserted
155.
What is a Mod N counter?
a)
A counter that counts from 0 to N-1
b)
A counter that counts from 1 to N
c)
A counter that counts from N-1 to 0
d)
A counter that counts in multiples of N
156.
How many flip-flops are required to design a Mod 5 counter?
a)
2 flip-flops
b)
2 flip-flops
c)
4 flip-flops
d)
5 flip-flops
157.
Which of the following counters is an example of a Mod 10 counter?
a)
Johnson counter
b)
Ring counter
c)
Decade counter
d)
BCD counter
158.
What is the advantage of using a Mod N counter?
a)
It reduces power consumption
b)
It provides more counting sequences
c)
) It requires fewer flip-flops
d)
It eliminates glitches in the output
159.
Which keyword is used to declare a flip flop in Verilog?
a)
reg
b)
wire
c)
input
d)
output
160.
How do you model a positive-edge-triggered D flip flop in Verilog?
a)
always @(posedge clk) Q <= D;
b)
always @(negedge clk) Q <= D;
c)
always @(clk) Q <= D;
d)
always @(D) Q <= D;
161.
Which type of flip flop has feedback from both its output and input?
a)
D flip flop
b)
T flip flop
c)
) JK flip flop
d)
JK flip flop
162.
In Verilog, how do you model a modulo-10 counter using a for loop?
a)
for (i=0; i<10; i=i+1) begin ... end
b)
for (i=1; i<=10; i=i+1) begin ... end
c)
for (i=0; i<=10; i=i+1) begin ... end
d)
for (i=1; i<10; i=i+1) begin ... end
163.
What is the purpose of a reset signal in counter modeling?
a)
It determines the type of counter (up, down, etc.)
b)
It controls the clock input of the counter
c)
It sets the counter to its initial state
d)
It enables the counting operation of the counter
164.
Which of the following represents the characteristic equation of a J-K flip flop?
a)
Q(t) = Q(t-1)
b)
Q(t) = J(t) ⊕ K(t)
c)
Q(t) = D(t)
d)
Q(t) = S(t) ⊕ R(t)
165.
In which format is data stored in shift registers?
a)
Parallel
b)
Serial
c)
Both parallel and serial
d)
None of the above
166.
hich type of shift register shifts data in a parallel-in, serial-out manner?
a)
SIPO
b)
SISO
c)
PISO
d)
PIPO
167.
How many outputs does a 4-bit ripple counter have?
a)
2
b)
4
c)
8
d)
16
168.
n a synchronous counter, all flip flops are triggered by the same ___________.
a)
Clock signal
b)
Reset signal
c)
Enable signal
d)
Data input
169.
The excitation table of a J-K flip flop shows the ___________.
a)
Next state of the flip flop
b)
Input conditions for each state
c)
Output conditions for each state
d)
Current state of the flip flop
170.
Which of the following is a valid Verilog code for a D flip flop?
a)
always @(posedge clk) Q <= D;
b)
always @(negedge clk) Q = D;
c)
always @(clk) Q = D;
d)
always @(D) Q = clk;
171.
How many flip flops are required to implement a 3-bit ripple counter?
a)
1
b)
2
c)
3
d)
4
172.
The conversion of a J-K flip flop to a D flip flop requires the addition of ___________.
a)
AND gates
b)
OR gates
c)
XOR gates
d)
NOT gates
173.
Which type of flip flop has an additional input called the "clock enable" input?
a)
S-R flip flop
b)
D flip flop
c)
J-K flip flop
d)
T flip flop
174.
Which of the following represents the characteristic equation of an S-R flip flop?
a)
Q(t) = S(t) ⊕ R(t)
b)
Q(t) = S(t) ⋅ R(t)
c)
Q(t) = S(t) + R(t)
d)
Q(t) = S(t) · R(t)
175.
Which type of flip flop is commonly used for frequency division?
a)
S-R flip flop
b)
D flip flop
c)
J-K flip flop
d)
T flip flop
176.
How many inputs does a J-K flip flop have?
a)
1
b)
2
c)
3
d)
4
177.
Which type of flip flop requires both a clock and a enable signal for operation?
a)
S-R flip flop
b)
D flip flop
c)
J-K flip flop
d)
T flip flop
178.
Which type of counter has a fixed sequence of states?
a)
Ripple counter
b)
Synchronous counter
c)
Up/down counter
d)
Ring counter
179.
What is the Verilog code for a positive edge-triggered D flip flop with asynchronous reset?
a)
always @(posedge clk) if (reset) Q <= 1'b0; else Q <= D;
b)
always @(negedge clk) if (reset) Q <= 1'b0; else Q <= D;
c)
always @(posedge clk) if (reset) Q = 1'b0; else Q = D;
d)
always @(negedge clk) if (reset) Q = 1'b0; else Q = D;
180.
Which type of shift register allows parallel loading of data?
a)
SIPO
b)
SISO
c)
PISO
d)
PIPO
181.
How many flip flops are required to implement a 5-bit synchronous counter?
a)
1
b)
2
c)
5
d)
8
182.
Which of the following is an example of a synchronous counter?
a)
Johnson counter
b)
Ring counter
c)
Binary counter
d)
Decade counter
183.
What is the Verilog code for a 4-bit ripple counter?
a)
always @(posedge clk) if (reset) Q <= 4'b0000; else Q <= Q + 1;
b)
always @(posedge clk) if (reset) Q <= 4'b0000; else Q <= Q - 1;
c)
always @(posedge clk) if (reset) Q <= 4'b1111; else Q <= Q + 1;
d)
always @(posedge clk) if (reset) Q <= 4'b1111; else Q <= Q - 1;
184.
Which type of shift register shifts data in a serial-in, parallel-out manner?
a)
SIPO
b)
SISO
c)
PISO
d)
PISO
185.
How many outputs does a 3-bit synchronous counter have?
a)
2
b)
4
c)
6
d)
8
186.
Which of the following is an example of a PIPO (Parallel-In, Parallel-Out) shift register?
a)
Shift register with serial input and parallel output
b)
Shift register with parallel input and serial output
c)
Shift register with serial input and serial output
d)
Shift register with parallel input and parallel output
187.
What is the Verilog code for a 3-bit synchronous counter using D flip flops?
a)
always @(posedge clk) if (reset) Q <= 3'b000; else Q <= Q + 1;
b)
always @(posedge clk) if (reset) Q <= 3'b000; else Q <= Q - 1;
c)
always @(posedge clk) if (reset) Q <= 3'b111; else Q <= Q + 1;
d)
always @(posedge clk) if (reset) Q <= 3'b111; else Q <= Q - 1;
188.
Which of the following flip flops is also known as a "toggle" flip flop?
a)
S-R flip flop
b)
D flip flop
c)
J-K flip flop
d)
T flip flop
189.
In a Master-Slave J-K flip flop, which edge triggers the Master flip flop?
a)
Positive edge
b)
Negative edge
c)
Both positive and negative edges
d)
No edge triggering, it's level triggered
190.
Which type of counter can count both upwards and downwards?
a)
Ripple counter
b)
Synchronous counter
c)
Up/down counter
d)
Ring counter
191.
What is the Verilog code for a 4-bit synchronous counter using T flip flops?
a)
always @(posedge clk) if (reset)
Q <= 4'b0000; else Q <= Q ^ 4'b1111;
b)
always @(posedge clk) if (reset)
Q <= 4'b0000; else Q <= Q + 1;
c)
always @(posedge clk) if (reset)
Q <= 4'b0000; else Q <= Q - 1;
d)
always @(posedge clk) if (reset)
Q <= 4'b0000; else Q <= ~Q;
192.
Which type of shift register allows both shifting and parallel loading of data?
a)
SIPO
b)
SISO
c)
PISO
d)
PIPO
193.
What is the Verilog code for a 3-bit ripple counter with asynchronous reset?
a)
always @(posedge clk) if (reset)
Q <= 3'b000; else Q <= Q + 1;
b)
always @(posedge clk) if (reset)
Q <= 3'b000; else Q <= Q - 1;
c)
always @(posedge clk) if (reset)
Q <= 3'b111; else Q <= Q + 1;
d)
always @(posedge clk) if (reset)
Q <= 3'b111; else Q <= Q - 1;
194.
Which type of flip flop is also known as a "data" flip flop?
a)
S-R flip flop
b)
D flip flop
c)
J-K flip flop
d)
T flip flop
195.
Transistor–transistor logic (TTL) is a class of digital circuits built from
a)
JFET only
b)
BJT
c)
resistors
d)
bjt and resistors
196.
TTL is called transistor–transistor logic because both the logic gating function and the
amplifying function are performed by
a)
Resistors
b)
Bipolar junction transistors
c)
One transistor
d)
Resistors and transistors respectively
197.
TTL was invented in 1961 by
a)
Baker clamp
b)
James L. Buie
c)
Chris Brown
d)
Frank Wanlass
198.
TTL inputs are the emitters of a
a)
Transistor-transistor logic
b)
Multiple-emitter transistor
c)
Resistor-transistor logic
d)
Diode-transistor logic
199.
TTL is a
a)
Current sinking
b)
Current sourcing
c)
Voltage sinking
d)
Voltage sourcing
200.
Standard TTL circuits operate with a __ volt power supply.
a)
2
b)
4
c)
5
d)
3
201.
TTL devices consume substantially ______ power than equivalent CMOS devices at rest.
a)
Less
b)
More
c)
Equal
d)
Very High
202.
A TTL gate may operate inadvertently as an
a)
Digital amplifier
b)
Analog amplifier
c)
Inverter
d)
Regulator
203.
The speed of ______ circuits is limited by the tendency of common emitter circuits to go into saturation.
a)
TTL
b)
ECL
c)
RTL
d)
DTL
204.
The full form of ECL is
a)
Emitter-collector logic
b)
Emitter-complementary logic
c)
Emitter-coupled logic
d)
Emitter-cored logic
205.
Which logic is the fastest of all the logic families?
a)
TTL
b)
ECL
c)
HTL
d)
DTL
206.
In an ECL the output is taken from
a)
Emitter
b)
Base
c)
Collector
d)
Junction of emitter and base
207.
The ECL behaves as
a)
NOT gate
b)
NOR gate
c)
NAND gate
d)
AND gate
208.
In ECL the fanout capability is
a)
High
b)
Low
c)
Zero
d)
Sometimes high and sometimes low
209.
ECL’s major disadvantage is that
a)
It requires more power
b)
It’s fanout capability is high
c)
It creates more noise
d)
It is slow
210.
The ECL circuits usually operates with
a)
Negative voltage
b)
Positive voltage
c)
Grounded voltage
d)
High Voltage
211.
The full form of CMOS is
a)
Capacitive metal oxide semiconductor
b)
Capacitive metallic oxide semiconductor
c)
Complementary metal oxide semiconductor
d)
Complemented metal oxide semiconductor
212.
CMOS behaves as a/an
a)
Adder
b)
Subtractor
c)
Inverter
d)
Comparator
213.
CMOS logic dissipates _______ power than NMOS logic circuits.
a)
More
b)
Less
c)
Equal
d)
Very High
214.
An important characteristic of a CMOS circuit is the
a)
Noise immunity
b)
Duality
c)
Symmetricity
d)
Noise Margin
215.
Which logic gate configuration is commonly used in CMOS design for its low power consumption?
a)
NOR gate
b)
NAND gate
c)
XOR gate
d)
AND-OR-Invert (AOI) gate
216.
Which of the following statements is true regarding CMOS technology?
a)
It is primarily used in high-power applications.
b)
It is immune to noise and interference.
c)
It consumes more power compared to other logic families.
d)
It is a bipolar transistor-based technology.
217.
In CMOS technology, what is the purpose of the PMOS transistor?
a)
To provide a low-resistance path to ground.
b)
To provide a high-resistance path to ground.
c)
To provide a low-resistance path to the power supply.
d)
To provide a high-resistance path to the power supply.
218.
In CMOS logic circuits, what is the purpose of the pull-up and pull-down networks?
a)
To ensure that both PMOS and NMOS transistors are always on
b)
To provide a high impedance path to ground and VDD
c)
To regulate the power supply voltage
d)
To minimize the propagation delay of the circuit
219.
Which type of logic gate typically has the longest propagation delay?
a)
AND gate
b)
OR gate
c)
XOR gate
d)
NOT gate
220.
What is transition time in a logic circuit?
a)
The time it takes for a logic gate to perform a computation
b)
The time it takes for a signal to travel from input to output
c)
The time it takes for a signal to transition between logic levels
d)
The time it takes for a logic circuit to power on and stabilize
221.
How does an increase in transition time affect the performance of a logic circuit?
a)
It increases the power consumption of the circuit.
b)
It decreases the complexity of the circuit.
c)
It reduces the maximum clock frequency that the circuit can support.
d)
It improves the noise immunity of the circuit.
222.
What does the power-delay product represent in a logic circuit?
a)
The power consumed by the circuit multiplied by the propagation delay
b)
The power efficiency of the circuit multiplied by the transition time
c)
The power consumed by the circuit divided by the propagation delay
d)
The power efficiency of the circuit divided by the transition time
223.
How does a decrease in the power-delay product affect the performance of a logic circuit?
a)
It decreases the power consumption of the circuit.
b)
It increases the complexity of the circuit.
c)
It reduces the maximum clock frequency that the circuit can support.
d)
It improves the noise immunity of the circuit.
224.
What does "fan-out" refer to in logic circuit design?
a)
The number of inputs a logic gate can accept
b)
The number of outputs a logic gate can drive
c)
The maximum clock frequency a circuit can support
d)
The power consumed by a logic gate
225.
What is the building block of a TTL inverter circuit?
a)
NAND gate
b)
NOR gate
c)
AND gate
d)
Transistor
226.
In a TTL inverter circuit, what is the purpose of the resistor connected to the base of the transistor?
a)
To provide biasing for the transistor
b)
To amplify the input signal
c)
To control the output voltage level
d)
To regulate the power supply
227.
In a TTL inverter circuit, what is the voltage level at the output when the input is at logic level "0"?
a)
High voltage (Vcc)
b)
Low voltage (0V)
c)
Floating voltage
d)
Varies based on the transistor used
228.
What is the typical voltage threshold for logic level transition in a TTL inverter circuit?
a)
0.2 volts
b)
0.8 volts
c)
2.0 volts
d)
3.3 volts
229.
Which of the following is a disadvantage of TTL inverter circuits?
a)
High power consumption
b)
Limited fan-out capability
c)
Incompatibility with other logic families
d)
Low noise immunity
230.
What is the basic structure of a CMOS inverter?
a)
One PMOS transistor and one NMOS transistor in series
b)
One PMOS transistor and one NMOS transistor in paralle
c)
Two PMOS transistors in series
d)
Two NMOS transistors in parallel
231.
Which of the following describes the operation of a CMOS inverter when the input is logic high(1)?
a)
The PMOS transistor is off, and the NMOS transistor is on
b)
The PMOS transistor is on, and the NMOS transistor is off
c)
Both the PMOS and NMOS transistors are off
d)
Both the PMOS and NMOS transistors are on
232.
In a CMOS inverter, what happens when the input voltage is at the threshold voltage(Vth) of the transisitors?
a)
The output voltage is at the threshold voltage as well
b)
The output voltage is at the positive power supply voltage (VDD)
c)
The output voltage is at ground (0V)
d)
The output voltage cannot be determined
233.
What is the advantage of using CMOS inverters in digital circuits?
a)
High speed and low power consumption
b)
High voltage gain
c)
Compatibility with bipolar transistors
d)
Ability to handle high currents
234.
What does TTL stand for in the context of digital electronics?
a)
Transistor-Transistor Logic
b)
Time-Triggered Logic
c)
Transmit-Transmit Loop
d)
Technical Transistor Logic
235.
Which of the following describes the basic structure of a TTL gate?
a)
Multiple MOS transistors in series
b)
One MOS transistor and one bipolar junction transistor in series
c)
One MOS transistor and one bipolar junction transistor in parallel
d)
Multiple MOS transistors in parallel
236.
In TTL gates, what is the logic level represented by a low voltage (logic 0)?
a)
VDD (positive power supply voltage)
b)
Ground (0V)
c)
VDD/2 (half of the positive power supply voltage)
d)
VSS (negative power supply voltage)
237.
Which component in a TTL gate provides current amplification?
a)
MOS transistor
b)
Bipolar junction transistor (BJT)
c)
Resistor
d)
Capacitor
238.
What is the advantage of using TTL gates in digital circuits?
a)
High noise immunity and robustness
b)
Low power consumption
c)
Compatibility with CMOS devices
d)
Ability to handle high-frequency signals
239.
Which of the following describes the basic structure of a CMOS gate?
a)
Multiple MOS transistors in series
b)
One MOS transistor and one bipolar junction transistor in series
c)
One PMOS transistor and one NMOS transistor in series
d)
Multiple PMOS and NMOS transistors in parallel
240.
.Which component in a CMOS gate is responsible for pulling the output voltage to the power supply rail?
a)
PMOS transistor
b)
NMOS transistor
c)
Resistor
d)
Capacitor
241.
What is the advantage of using CMOS gates in digital circuits?
a)
Low power consumption and high noise immunity
b)
High voltage gain
c)
Compatibility with TTL devices
d)
Ability to handle high-frequency signals
242.
Which of the following statements about TTL (Transistor-Transistor Logic) NAND gate is true?
a)
It is a combination of multiple NAND gates.
b)
It is a combination of NAND and NOR gates.
c)
It is a digital logic gate that implements the logical NAND function
d)
It is a type of analog gate used in signal amplification
243.
TTL NAND gates typically operate with a supply voltage of:
a)
3.3 volts
b)
5 volts
c)
12 volts
d)
Variable voltage based on the application
244.
In TTL NAND gate, the output is low when:
a)
Both inputs are low
b)
Both inputs are high
c)
One input is low and the other is high
d)
Output is always high in a TTL NAND gate
245.
The TTL NAND gate has __ input(s) and __ output(s).
a)
2 inputs, 1 output
b)
1 input, 2 outputs
c)
3 inputs, 1 output
d)
1 input, 1 output
246.
In CMOS technology, a NAND gate is constructed using:
a)
NMOS (N-channel Metal-Oxide-Semiconductor) transistors only
b)
PMOS (P-channel Metal-Oxide-Semiconductor) transistors only
c)
Both NMOS and PMOS transistors
d)
Bipolar junction transistors (BJTs)
247.
The output of a CMOS NAND gate is high when:
a)
Both inputs are low
b)
Both inputs are high
c)
One input is low and the other is high
d)
Output is always high in a CMOS NAND gate
248.
The logic symbol for a CMOS NAND gate is represented by:
a)
A triangle
b)
A circle
c)
A rectangle with a concave side
d)
A rectangle with a convex side
249.
The CMOS NAND gate is commonly used in digital circuits for:
a)
Logic inversion
b)
Signal amplification
c)
Data storage
d)
Data storage
250.
In CMOS technology, NAND gate stands for
a)
Negative AND
b)
Non-AND
c)
NAND NOT
d)
Non-inverted AND
251.
The output of a NAND gate is LOW only when:
a)
Both inputs are HIGH
b)
Both inputs are LOW
c)
Either input is LOW
d)
Either input is HIGH
252.
In CMOS technology, NOR gate stands for:
a)
Negative OR
b)
Non-OR
c)
NOR NOT
d)
Non-inverted OR
253.
The output of a NOR gate is HIGH only when:
a)
Both inputs are HIGH
b)
Both inputs are LOW
c)
Either input is LOW
d)
Either input is HIGH
254.
In a CMOS NOR gate, the pull-down network consists of:
a)
PMOS transistors
b)
NMOS transistors
c)
Both PMOS and NMOS transistors
d)
Resistors
100 %
