WorksheetsFlip Flop Revision Test
Total questions: 55
Worksheet time: 34mins
In SR Flip Flops, given the inputs S = 0, R =0, and Present state Qn = 0. Find the Next State Qn+1 .
01
1
Dont care
0
In SR Flip flop, given the inputs S=0, R=1, and Present state Qn=1, Then next state Qn+1 =
0
1
Dont care
In SR Flip Flops, given the inputs S=1, R=1, and present state Qn= 1, then
1
0
Indeterminant
In JK Flip Flops, given the inputs J=1, K=1, and present state Qn= 1, then
1
0
Indeterminant
In JK Flip Flops, given the inputs J=1, K=0, and present state Qn= 1, then
1
0
Indeterminant
In D Flip Flops, given the inputs D=1,present state Qn= 1, then
1
0
Indeterminant
In T Flip Flops, given the inputs T=1,present state Qn= 1, then
1
0
Indeterminant
In T Flip Flops, given the inputs T=0,present state Qn= 1, then
1
0
Indeterminant
Given SR excitation table with present state Qn=0, next state Qn+1=1, then find the inputs
S=0 , R = 1
S=1 , R= 0
S=0 , R = x
S=x , R= 0
Given JK excitation table with inputs Qn=1, Qn+1=0, then find the inputs J and K
J=x , K = 1
J=1 , K = x
J=0 , K= x
J=x ,K = 0
Given D excitation table with inputs Qn=0,Qn+1=1 then find the input D
1
0
dont care
Given T excitation table with inputs Qn=1,Qn+1=1 then find the inputs
1
0
dont care
In D Flip Flops, given the inputs D=0,present state Qn= 1, then
1
0
Indeterminant
In SR flip flops , when the given inputs are S=1 and R =1 , then next state will be
No change
Reset
Indeterminant
Toggle
In JK flip flops , when the given inputs are J=1 and K =1 , then next state will
Not change
Reset
Indeterminant
Toggle
Clock
Q = D'
Q
In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
The flip-flops which has not any invalid states are _____________
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, T
Sequential circuit contains
a) No memory element
b) Atleast one memory element
c) All inputs applied simultaneously
T Flip flop is used as
Transfer data circuit
Toggle switch
Time delay switch
The advantage of a J-K flip-flop over an S-R FF is that ________.
A.it does not require a clock input
B.it has only one output
C.it has no invalid states
Following flip flop is used to eliminate race around problem
SR Flip flop
JK Flip flop
Master Slave Flip flop
Number of inputs for D flip flop
3
2
1
In a J-K flip-flop, if J=K the resulting flip-flop is referred to as
D flip-flop
T flip-flop
S-K flip-flop
The flip-flop is only activated by _____________
Positive edge trigger
Negative edge trigger
Either positive or Negative edge trigger
The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
Combinational Circuits
Sequential Circuits
None of the above
Latches consist of
inductors
inverters
timing generators
frequency generators
Inverters in latch form a feedback loop which is always
Positive
Negative
Changing
Infinite
Latch is a bistable circuit having
one complementary output
two complementary outputs
three complementary outputs
four complementary outputs
Latch together with a triggering circuit form a
inductor
flip flop
timing generator
sine generator
Latch doesn't contain
state input
state output
inverter
clock
D flip flop tracks the
input
output
source
ground
In SR flip flop, input labeled 'S' stands for
Systematic
Static
Set
Stable
D flip flop consists of
one inverter
two inverters
one buffer
two buffers
Logic depends only on present value of input is
combinational logic
sequential logic
systematic logic
correctional logic
Bistable circuit can be used to store information of
one bit
two bits
three bits
four bits
In the toggle mode, a JK flip-flop has
J = 0, K = 1
J = 1, K = 0
J = 1, K = 1
J = 0, K = 0
A digital circuit that can store only one bit is a
NAND Gate
Flip Flop
Adder
Priority Encoder
In Sequential Circuit the output states depend upon
Past Input States
Present Input States
Control Circuit
Present as well as past input
D Flip Flop can be used as
Delay Switch
Differentiator
Data Selector
Divider Circuit
The purpose of clock input to a flip flop is to
Clear the device
Set the device
Cause the output to change its state depending upon the inputs
Cause the input to toggle
A feature that distinguishes the JK flip flop from the D flip flop is __________
Toggle Condition
Preset Input
NAND Gates
Type of Clock
T Flip Flop is used as a __________
Delay Switch
Transfer data Switch
Toggle Switch
Transit Switch
When both inputs of a S-R flip-flop is in high state, the outputs (Q and Q') will be
1 and 0
0 and 1
Invalid
In Toggle State
There are basically ____________ different types of flip flops.
Four
Five
Six
Three
Which is the prohibited state/ condition in S-R latch and needs to be avoided due to unpredictable nature of output?
S=R=0
S=0 and R=1
S=1 and R=0
S=R=1
